On 22/09/2026 12:12, Richard Biener wrote:
On Mon, Sep 21, 2026 at 1:39 PM Andrew Stubbs <[email protected]> wrote:
This patch replaces the separate macros BASE_REG_CLASS, MODE_BASE_REG_CLASS,
MODE_BASE_REG_REG_CLASS, MODE_CODE_BASE_REG_CLASS, and INSN_BASE_REG_CLASS
into a single hook: TARGET_BASE_REG_CLASS.
It also adds a new parameter, MEM, that is intended to be used by AMD GCN
soon. Adding this is the main motivation for changing the hook, but this patch
should not change the behaviour of anything, yet.
Rather than replace every definition of these macros in every backend, this
keeps those as the default implementation of the hook. INSN_BASE_REG_CLASS
had only one caller (i386), and was the one that I was interesting in
extending, so it has been entirely deleted.
(This patch superceeds my previous patch for INSN_BASE_REG_CLASS.)
This patch was largely generated using AI, but as the edits are mechanical
changes with no real new content I do not believe them to be "legally
significant" (a lot of lines are touched, but its the same thing repeated).
LGTM, but - how did you test it? patchworks shows simplebootstrap passed
on arm and aarch64.
Sorry, I should have said.
I did a full dejagnu test on x86_64-linux-gnu and on amdgcn-amdhsa.
There were no regressions.
Is that OK?
Thanks
Andrew
