Hi Andrew,
After review with Jakub the patchset you tested here has had some
changes in the target specific ends.
All around taking things
The new patch with the relevant target-specific changes is here
https://gcc.gnu.org/pipermail/gcc-patches/2026-August/728743.html
Which Jakub has OK'd with formatting nits here:
https://gcc.gnu.org/pipermail/gcc-patches/2026-September/731286.html
Could you take a look and double-check that this seems valid to you?
Regards,
Matthew
On 11/10/25 16:13, Andrew Stubbs wrote:
External email: Use caution opening links or attachments
On 10/11/2025 10:06, [email protected] wrote:
Points to highlight:
- I have not got a testing environment for gcn/rtems/nvptx targets.
I have made the changes that should allow them to build and checked
that they do indeed build, but would appreciate relevant maintainers
performing the actual testing.
I have built an x86_64/amdgcn toolchain with these 4 patches applied,
and run the libgomp testsuite with no regressions.
I can't comment on the wider patch(set), but the amdgcn portion looks
like a reasonable no-op implementation. The AMD ISA does not have a
barrier instruction capable of synchronizing a subset of threads (it's
all or nothing).
Andrew
