On Wed Sep 23, 2026 at 2:11 AM PDT, Richard Biener wrote:
> vec_to_scalar costs a lane extraction which might be lane zero
> from a vector to a scalar.  The following makes us account for
> the extra cost when the target is a GPR.
>
> I chose to not limit the testcase to any tuning/ISA, it shouldn't
> be vectorized for any combination.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu.
>
> OK?
Ok.

BTW, I realized that could be the reason H.J posted
https://gcc.gnu.org/pipermail/gcc-patches/2026-September/730504.html
And this commit should address PR127268.

>
> HJ, your patches contain more testcases, if some were added that
> pass on an unpatched compiler, can you post/push those separately
> so we can see whether those regress?  I suspect some of your
> patch complexity was because of cases regressing with simple
> adjustments like this?
>
>       * config/i386/i386.cc (ix86_default_vector_cost): For
>       integer mode vec_to_scalar add sse_to_integer cost.
>
>       * gcc.target/i386/vect-bb-reduc-1.c: New testcase.
> ---
>  gcc/config/i386/i386.cc                         |  3 +++
>  gcc/testsuite/gcc.target/i386/vect-bb-reduc-1.c | 13 +++++++++++++
>  2 files changed, 16 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/i386/vect-bb-reduc-1.c
>
> diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
> index 705ebb6c014..89f7b68d046 100644
> --- a/gcc/config/i386/i386.cc
> +++ b/gcc/config/i386/i386.cc
> @@ -26045,6 +26045,9 @@ ix86_default_vector_cost (enum vect_cost_for_stmt 
> type_of_cost,
>          return COSTS_N_INSNS (ix86_cost->sse_store[index]) / 2;
>  
>        case vec_to_scalar:
> +     return (ix86_vec_cost (mode, ix86_cost->sse_op)
> +             + (fp ? 0 : COSTS_N_INSNS (ix86_cost->sse_to_integer) / 2));
> +
>        case scalar_to_vec:
>          return ix86_vec_cost (mode, ix86_cost->sse_op);
>  
> diff --git a/gcc/testsuite/gcc.target/i386/vect-bb-reduc-1.c 
> b/gcc/testsuite/gcc.target/i386/vect-bb-reduc-1.c
> new file mode 100644
> index 00000000000..c8efbb8c24f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/vect-bb-reduc-1.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +extern unsigned char *var1;
> +extern unsigned short var2;
> +void
> +func (void)
> +{
> +  var2 = var1[1] + var1[0];
> +}
> +
> +/* We do not want to vectorize the reduction.  */
> +/* { dg-final { scan-assembler-not "xmm" } } */
> -- 
> 2.51.0

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