riscv_rvv_vector_bits(N) currently requires -mrvv-vector-bits=zvl and
N == VLEN * LMUL, so an object is correctly sized only when the hardware
VLEN matches the zvl it was compiled for; on a larger VLEN a whole-register
access overruns it.
This series allows a data typedef to use any power-of-two N that is a
multiple of the element size and no greater than TARGET_MIN_VLEN scaled by
the type's LMUL, with or without -mrvv-vector-bits=zvl. Such a type gets a
VLS mode of exactly N bits, so accesses are VL-limited and the code runs on
any VLEN >= TARGET_MIN_VLEN. It is a prefix of the register holding the
RVV type it was written against and converts to and from that type alone,
which is what lets it be passed to the existing VLA intrinsics. Mask types
stay on the strict path. Every case this accepts was an error before, so
no program that compiles today changes meaning.
Patch 1 is the only one that touches generic code, and the one I would
most like a second opinion on. vector_types_convertible_p rejects
conversions between fixed-length and scalable vector types when their
TYPE_SIZEs are not comparable -- here an INTEGER_CST against a
POLY_INT_CST -- and TARGET_CONVERT_TO_TYPE cannot help, because
convert_for_assignment checks compatibility first. The new hook defaults
to false, so other targets are unaffected; aarch64 does not need it, since
arm_sve_vector_bits requires N to equal the whole register.
Bootstrapped and regtested on x86_64-pc-linux-gnu with the stage2/stage3
comparison clean and no change in the set of failures against the base
revision. Also built as a cross to riscv64-unknown-elf at each commit in
the series, with no new failures in the RVV testsuite.
Monk Chiang (3):
c-family: Add TARGET_VECTOR_TYPES_CONVERTIBLE_P hook
RISC-V: Allow riscv_rvv_vector_bits to be shorter than the vector
register
RISC-V: Convert between shorter riscv_rvv_vector_bits types and RVV
types
gcc/c-family/c-common.cc | 3 +
gcc/config/riscv/riscv-builtins.cc | 24 ++
gcc/config/riscv/riscv-c.cc | 7 +
gcc/config/riscv/riscv-protos.h | 9 +
gcc/config/riscv/riscv-vector-builtins.cc | 96 +++++++
gcc/config/riscv/riscv.cc | 235 +++++++++++++++++-
gcc/doc/extend.texi | 42 ++++
gcc/doc/tm.texi | 11 +
gcc/doc/tm.texi.in | 2 +
gcc/hooks.cc | 7 +
gcc/hooks.h | 1 +
gcc/target.def | 14 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-1.C | 44 ++++
.../riscv/rvv/base/riscv_rvv_vector_bits-2.C | 18 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-3.C | 24 ++
.../g++.target/riscv/rvv/pch/pch.exp | 45 ++++
.../riscv/rvv/pch/riscv_rvv_vector_bits-1.C | 11 +
.../riscv/rvv/pch/riscv_rvv_vector_bits-1.Hs | 5 +
.../riscv/rvv/base/riscv_rvv_vector_bits-19.c | 36 +++
.../riscv/rvv/base/riscv_rvv_vector_bits-20.c | 11 +
.../riscv/rvv/base/riscv_rvv_vector_bits-21.c | 18 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-23.c | 57 +++++
.../riscv/rvv/base/riscv_rvv_vector_bits-24.c | 25 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-25.c | 9 +
.../riscv/rvv/base/riscv_rvv_vector_bits-26.c | 9 +
.../riscv/rvv/base/riscv_rvv_vector_bits-27.c | 21 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-28.c | 22 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-29.c | 21 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-3.c | 2 +-
.../riscv/rvv/base/riscv_rvv_vector_bits-30.c | 16 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-31.c | 43 ++++
.../riscv/rvv/base/riscv_rvv_vector_bits-32.c | 11 +
.../riscv/rvv/base/riscv_rvv_vector_bits-34.c | 26 ++
.../riscv/rvv/base/riscv_rvv_vector_bits-35.c | 7 +
.../riscv/rvv/base/riscv_rvv_vector_bits-36.c | 9 +
.../riscv/rvv/base/riscv_rvv_vector_bits-4.c | 2 +-
.../riscv/rvv/base/riscv_rvv_vector_bits-5.c | 2 +-
.../riscv/rvv/base/riscv_rvv_vector_bits-6.c | 2 +-
38 files changed, 932 insertions(+), 15 deletions(-)
create mode 100644
gcc/testsuite/g++.target/riscv/rvv/base/riscv_rvv_vector_bits-1.C
create mode 100644
gcc/testsuite/g++.target/riscv/rvv/base/riscv_rvv_vector_bits-2.C
create mode 100644
gcc/testsuite/g++.target/riscv/rvv/base/riscv_rvv_vector_bits-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/pch/pch.exp
create mode 100644
gcc/testsuite/g++.target/riscv/rvv/pch/riscv_rvv_vector_bits-1.C
create mode 100644
gcc/testsuite/g++.target/riscv/rvv/pch/riscv_rvv_vector_bits-1.Hs
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-19.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-20.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-21.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-23.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-24.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-25.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-26.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-27.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-28.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-29.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-30.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-31.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-34.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-35.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-36.c
base-commit: 37c33c6a1c86ba88db8f0cf2e398374f0e501038
--
2.54.0
