Hi,
Right now we only show an error if the expansion of a builtin fails.
But there is builtin code that get optimized away before expansion and
never shows an error message. It's not strictly wrong code but at least
surprising and will mislead compilation checks.
This patch just copies the checks of expand_builtin to
check_builtin_call. We don't have the exact same expression of the
affected call available at that point, though. The basic fndecl just
contains the function name and not its arguments. We can reconstruct
the call but in my tests there were always slight difference to the
expand-time diagnostic. Therefore I adjusted the test expectations
instead. Quite a few, unfortunately...
Regtested on rv64gcv_zvl512b.
Regards
Robin
PR target/127553
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc
(validate_instance_type_required_extensions):
Add location param for logging.
(expand_builtin): Pass location.
(check_builtin_call): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/bug-9.c: Adjust test expectation.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-10.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-2.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-3.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-4.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-5.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-6.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-7.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-8.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-9.c: Ditto.
* gcc.target/riscv/rvv/base/pr114988-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr114988-2.c: Ditto.
* gcc.target/riscv/rvv/base/pr120436.c: Ditto.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c:
* gcc.target/riscv/pr127553.c: New test.
---
gcc/config/riscv/riscv-vector-builtins.cc | 46 +++++++++++++------
gcc/testsuite/gcc.target/riscv/pr127553.c | 13 ++++++
.../gcc.target/riscv/rvv/base/bug-9.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-1.c | 2 +-
.../rvv/base/intrinsic_required_ext-10.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-2.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-3.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-4.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-5.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-6.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-7.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-8.c | 2 +-
.../riscv/rvv/base/intrinsic_required_ext-9.c | 2 +-
.../gcc.target/riscv/rvv/base/pr114988-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pr114988-2.c | 2 +-
.../gcc.target/riscv/rvv/base/pr120436.c | 6 +--
.../target_attribute_v_with_intrinsic-17.c | 2 +-
.../target_attribute_v_with_intrinsic-18.c | 2 +-
.../target_attribute_v_with_intrinsic-19.c | 2 +-
.../target_attribute_v_with_intrinsic-20.c | 2 +-
.../target_attribute_v_with_intrinsic-21.c | 2 +-
.../target_attribute_v_with_intrinsic-22.c | 2 +-
.../target_attribute_v_with_intrinsic-23.c | 2 +-
.../target_attribute_v_with_intrinsic-24.c | 2 +-
.../target_attribute_v_with_intrinsic-25.c | 2 +-
.../target_attribute_v_with_intrinsic-26.c | 2 +-
.../target_attribute_v_with_intrinsic-27.c | 2 +-
.../target_attribute_v_with_intrinsic-28.c | 2 +-
.../target_attribute_v_with_intrinsic-29.c | 2 +-
.../target_attribute_v_with_intrinsic-3.c | 2 +-
.../target_attribute_v_with_intrinsic-7.c | 2 +-
.../target_attribute_v_with_intrinsic-8.c | 2 +-
32 files changed, 78 insertions(+), 45 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr127553.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index a7e5c24281f..64e8127f1b5 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -5724,56 +5724,56 @@ gimple_fold_builtin (unsigned int code,
gimple_stmt_iterator *gsi, gcall *stmt)
static bool
validate_instance_type_required_extensions (const rvv_type_info type,
- tree exp)
+ location_t location, tree fndecl)
{
uint64_t exts = type.required_extensions;
if ((exts & RVV_REQUIRE_ELEN_BF_16)
&& !TARGET_VECTOR_ELEN_BF_16_P (riscv_vector_elen_flags))
{
- error_at (EXPR_LOCATION (exp),
+ error_at (location,
"built-in function %qE requires the "
"zvfbfmin or zvfbfwma ISA extension",
- exp);
+ fndecl);
return false;
}
if ((exts & RVV_REQUIRE_ELEN_FP_16)
&& !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags))
{
- error_at (EXPR_LOCATION (exp),
+ error_at (location,
"built-in function %qE requires the "
"zvfhmin or zvfh ISA extension",
- exp);
+ fndecl);
return false;
}
if ((exts & RVV_REQUIRE_ELEN_FP_32)
&& !TARGET_VECTOR_ELEN_FP_32_P (riscv_vector_elen_flags))
{
- error_at (EXPR_LOCATION (exp),
+ error_at (location,
"built-in function %qE requires the "
"zve32f, zve64f, zve64d or v ISA extension",
- exp);
+ fndecl);
return false;
}
if ((exts & RVV_REQUIRE_ELEN_FP_64)
&& !TARGET_VECTOR_ELEN_FP_64_P (riscv_vector_elen_flags))
{
- error_at (EXPR_LOCATION (exp),
+ error_at (location,
"built-in function %qE requires the zve64d or v ISA extension",
- exp);
+ fndecl);
return false;
}
if ((exts & RVV_REQUIRE_ELEN_64)
&& !TARGET_VECTOR_ELEN_64_P (riscv_vector_elen_flags))
{
- error_at (EXPR_LOCATION (exp),
+ error_at (location,
"built-in function %qE requires the "
"zve64x, zve64f, zve64d or v ISA extension",
- exp);
+ fndecl);
return false;
}
@@ -5797,12 +5797,14 @@ expand_builtin (unsigned int code, tree exp, rtx target)
{
error_at (EXPR_LOCATION (exp),
"built-in function %qE requires the %qs ISA extension",
- exp,
+ rfn->decl,
required_ext_to_isa_name (rfn->required));
return target;
}
- if (!validate_instance_type_required_extensions (rfn->instance.type, exp))
+ if (!validate_instance_type_required_extensions (rfn->instance.type,
+ EXPR_LOCATION (exp),
+ rfn->decl))
return target;
return function_expander (rfn->instance, rfn->decl, exp, target).expand ();
@@ -5822,6 +5824,24 @@ check_builtin_call (location_t location,
vec<location_t>, unsigned int code,
registered_function *rfn = lookup_registered_function (code);
if (!rfn)
return false;
+
+ /* Only check resolved functions. */
+ if (!rfn->overloaded_p)
+ {
+ if (!required_extensions_specified (rfn->required))
+ {
+ error_at (location,
+ "built-in function %qE requires the %qs ISA extension",
+ fndecl,
+ required_ext_to_isa_name (rfn->required));
+ return false;
+ }
+
+ if (!validate_instance_type_required_extensions (rfn->instance.type,
+ location, fndecl))
+ return false;
+ }
+
return function_checker (location, rfn->instance, fndecl,
TREE_TYPE (rfn->decl), nargs, args).check ();
}
diff --git a/gcc/testsuite/gcc.target/riscv/pr127553.c
b/gcc/testsuite/gcc.target/riscv/pr127553.c
new file mode 100644
index 00000000000..9747c20ec94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr127553.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -march=rv64gc" } */
+
+#include <riscv_vector.h>
+#include <stdint.h>
+#include <stddef.h>
+
+int main() {
+ uint8_t val = 3, dup[8];
+ size_t vl = __riscv_vsetvl_e8m1(8); /* { dg-error "built-in function
'__riscv_vsetvl_e8m1' requires the 'v' ISA extension" } */
+ vuint8m1_t v = __riscv_vmv_v_x_u8m1(val, vl); /* { dg-error "built-in
function '__riscv_vmv_v_x_u8m1' requires the 'v' ISA extension" } */
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
index f7c9ad10ccb..b3d27010966 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
@@ -7,7 +7,7 @@
vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl)
{
- return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl);
+ return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl); /* { dg-error "built-in
function '__riscv_vfadd_vv_f16m1_rm' requires the zvfhmin or zvfh ISA
extension" } */
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-1.c
index 143a3d66016..7958d4f1f76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-1.c
@@ -6,5 +6,5 @@
size_t
test_3 (size_t vl)
{
- return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function
'__riscv_vsetvl_e8m4\(vl\)' requires the 'v' ISA extension} } */
+ return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function
'__riscv_vsetvl_e8m4' requires the 'v' ISA extension} } */
}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-10.c
index b0a9851d4c7..b5d163af1a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-10.c
@@ -7,5 +7,5 @@ vuint32m1_t
__attribute__((target("arch=+v")))
test_1 (vuint32m1_t op_1, vuint32m1_t op_2, size_t vl)
{
- return __riscv_vsm3me_vv_u32m1 (op_1, op_2, vl); /* { dg-error {built-in
function '__riscv_vsm3me_vv_u32m1\(op_1, op_2, vl\)' requires the 'zvksh' ISA
extension} } */
+ return __riscv_vsm3me_vv_u32m1 (op_1, op_2, vl); /* { dg-error {built-in
function '__riscv_vsm3me_vv_u32m1' requires the 'zvksh' ISA extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-2.c
index 20ab9775a1e..82ae95d8410 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-2.c
@@ -7,5 +7,5 @@ vuint32m1_t
__attribute__((target("arch=+v")))
test_1 (vuint32m1_t op_1, vuint32m1_t op_2, size_t vl)
{
- return __riscv_vandn_vv_u32m1 (op_1, op_2, vl); /* { dg-error {built-in
function '__riscv_vandn_vv_u32m1\(op_1, op_2, vl\)' requires the 'zvbb or
zvkb' ISA extension} } */
+ return __riscv_vandn_vv_u32m1 (op_1, op_2, vl); /* { dg-error {built-in
function '__riscv_vandn_vv_u32m1' requires the 'zvbb or zvkb' ISA extension} }
*/
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-3.c
index 9b7d37f5b33..2128c543ee5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-3.c
@@ -7,5 +7,5 @@ vuint32m1_t
__attribute__((target("arch=+v")))
test_1 (vuint32m1_t op_1, size_t vl)
{
- return __riscv_vclz_v_u32m1 (op_1, vl); /* { dg-error {built-in function
'__riscv_vclz_v_u32m1\(op_1, vl\)' requires the 'zvbb' ISA extension} } */
+ return __riscv_vclz_v_u32m1 (op_1, vl); /* { dg-error {built-in function
'__riscv_vclz_v_u32m1' requires the 'zvbb' ISA extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-4.c
index fdaab62b17d..3110e278edb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-4.c
@@ -7,5 +7,5 @@ vuint64m1_t
__attribute__((target("arch=+v")))
test_1 (vuint64m1_t op_1, vuint64m1_t op_2, size_t vl)
{
- return __riscv_vclmul_vv_u64m1 (op_1, op_2, vl); /* { dg-error {built-in
function '__riscv_vclmul_vv_u64m1\(op_1, op_2, vl\)' requires the 'zvbc' ISA
extension} } */
+ return __riscv_vclmul_vv_u64m1 (op_1, op_2, vl); /* { dg-error {built-in
function '__riscv_vclmul_vv_u64m1' requires the 'zvbc' ISA extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-5.c
index 6a4bb431f4a..77525ce8673 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-5.c
@@ -7,5 +7,5 @@ vuint32m1_t
__attribute__((target("arch=+v")))
test_1 (vuint32m1_t dest, vuint32m1_t op_1, vuint32m1_t op_2, size_t vl)
{
- return __riscv_vghsh_vv_u32m1 (dest, op_1, op_2, vl); /* { dg-error
{built-in function '__riscv_vghsh_vv_u32m1\(dest, op_1, op_2, vl\)' requires
the 'zvkg' ISA extension} } */
+ return __riscv_vghsh_vv_u32m1 (dest, op_1, op_2, vl); /* { dg-error
{built-in function '__riscv_vghsh_vv_u32m1' requires the 'zvkg' ISA extension}
} */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-6.c
index 943a2cf653b..6df436ad616 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-6.c
@@ -7,5 +7,5 @@ vuint32m1_t
__attribute__((target("arch=+v")))
test_1 (vuint32m1_t dest, vuint32mf2_t op_1, size_t vl)
{
- return __riscv_vaesef_vs_u32mf2_u32m1 (dest, op_1, vl); /* { dg-error
{built-in function '__riscv_vaesef_vs_u32mf2_u32m1\(dest, op_1, vl\)'
requires the 'zvkned' ISA extension} } */
+ return __riscv_vaesef_vs_u32mf2_u32m1 (dest, op_1, vl); /* { dg-error
{built-in function '__riscv_vaesef_vs_u32mf2_u32m1' requires the 'zvkned' ISA
extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-7.c
index c2ccb739f6e..d5d65fe6a60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-7.c
@@ -7,5 +7,5 @@ vuint32m1_t
__attribute__((target("arch=+v")))
test_1 (vuint32m1_t dest, vuint32m1_t op_1, vuint32m1_t op_2, size_t vl)
{
- return __riscv_vsha2ms_vv_u32m1 (dest, op_1, op_2, vl); /* { dg-error
{built-in function '__riscv_vsha2ms_vv_u32m1\(dest, op_1, op_2, vl\)'
requires the 'zvknha or zvknhb' ISA extension} } */
+ return __riscv_vsha2ms_vv_u32m1 (dest, op_1, op_2, vl); /* { dg-error
{built-in function '__riscv_vsha2ms_vv_u32m1' requires the 'zvknha or zvknhb'
ISA extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-8.c
index e4312cc0530..1a026e2f7a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-8.c
@@ -7,5 +7,5 @@ vuint64m1_t
__attribute__((target("arch=+v")))
test_1 (vuint64m1_t dest, vuint64m1_t op_1, vuint64m1_t op_2, size_t vl)
{
- return __riscv_vsha2ms_vv_u64m1 (dest, op_1, op_2, vl); /* { dg-error
{built-in function '__riscv_vsha2ms_vv_u64m1\(dest, op_1, op_2, vl\)'
requires the 'zvknhb' ISA extension} } */
+ return __riscv_vsha2ms_vv_u64m1 (dest, op_1, op_2, vl); /* { dg-error
{built-in function '__riscv_vsha2ms_vv_u64m1' requires the 'zvknhb' ISA
extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-9.c
index 442d4917053..ea35b3d7e45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic_required_ext-9.c
@@ -7,5 +7,5 @@ vuint32m1_t
__attribute__((target("arch=+v")))
test_1 (vuint32m1_t op_1, size_t vl)
{
- return __riscv_vsm4k_vi_u32m1 (op_1, 0, vl); /* { dg-error {built-in
function '__riscv_vsm4k_vi_u32m1\(op_1, 0, vl\)' requires the 'zvksed' ISA
extension} } */
+ return __riscv_vsm4k_vi_u32m1 (op_1, 0, vl); /* { dg-error {built-in
function '__riscv_vsm4k_vi_u32m1' requires the 'zvksed' ISA extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
index b8474804c88..b797d5996b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
@@ -5,5 +5,5 @@
vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t vl)
{
- return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl); /* { dg-error {built-in
function '__riscv_vfwsub_wf_f32mf2\(vs2, rs1, vl\)' requires the zvfhmin or
zvfh ISA extension} } */
+ return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl); /* { dg-error {built-in
function '__riscv_vfwsub_wf_f32mf2' requires the zvfhmin or zvfh ISA extension}
} */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c
index 49aa3141af3..7491359c011 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c
@@ -5,5 +5,5 @@
vfloat32mf2_t test_vfwadd_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t vl)
{
- return __riscv_vfwadd_wf_f32mf2(vs2, rs1, vl); /* { dg-error {built-in
function '__riscv_vfwadd_wf_f32mf2\(vs2, rs1, vl\)' requires the zvfhmin or
zvfh ISA extension} } */
+ return __riscv_vfwadd_wf_f32mf2(vs2, rs1, vl); /* { dg-error {built-in
function '__riscv_vfwadd_wf_f32mf2' requires the zvfhmin or zvfh ISA extension}
} */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c
index d22091e5949..3ebdf3562df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c
@@ -8,9 +8,9 @@
#include "riscv_vector.h"
void
-clean_subreg (int32_t *in, int32_t *out, size_t m) /* { dg-error {this
operation requires the RVV ISA extension} } */
+clean_subreg (int32_t *in, int32_t *out, size_t m)
{
vint16m8_t v24, v8, v16;
- vint32m8_t result = __riscv_vle32_v_i32m8 (in, 32); /* { dg-error {built-in
function '__riscv_vle32_v_i32m8\(in, 32\)' requires the 'v' ISA extension} } */
- vint32m1_t v0 = __riscv_vget_v_i32m8_i32m1 (result, 0);
+ vint32m8_t result = __riscv_vle32_v_i32m8 (in, 32); /* { dg-error {built-in
function '__riscv_vle32_v_i32m8' requires the 'v' ISA extension} } */
+ vint32m1_t v0 = __riscv_vget_v_i32m8_i32m1 (result, 0); /* { dg-error
{built-in function '__riscv_vget_v_i32m8_i32m1' requires the 'v' ISA extension}
} */
}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
index ebe31f5c961..9c5904cddc6 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
@@ -7,7 +7,7 @@ vint64m1_t
__attribute__((target("arch=+zve32x")))
test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
{
- return __riscv_vadd_vv_i64m1 (a, b, vl);
+ return __riscv_vadd_vv_i64m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vadd_vv_i64m1' requires the zve64x, zve64f, zve64d or v ISA extension"
} */
}
/* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or
v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
index 7e9a101795d..abb7e8014c7 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
@@ -7,7 +7,7 @@ vfloat32m1_t
__attribute__((target("arch=+zve32x")))
test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f32m1 (a, b, vl);
+ return __riscv_vfadd_vv_f32m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f32m1' requires the zve32f, zve64f, zve64d or v ISA
extension" } */
}
/* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d
or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
index b5354f4291f..63b350f5ecc 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
@@ -7,7 +7,7 @@ vfloat16m1_t
__attribute__((target("arch=+zve32x")))
test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f16m1 (a, b, vl);
+ return __riscv_vfadd_vv_f16m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f16m1' requires the zvfhmin or zvfh ISA extension" } */
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
index c1a574d5e29..a630a02c029 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
@@ -7,7 +7,7 @@ vfloat64m1_t
__attribute__((target("arch=+zve32x")))
test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f64m1 (a, b, vl);
+ return __riscv_vfadd_vv_f64m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f64m1' requires the zve64d or v ISA extension" } */
}
/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
index 62c2815fdad..a6a39029b39 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
@@ -7,7 +7,7 @@ vint64m1_t
__attribute__((target("arch=+zve32f")))
test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
{
- return __riscv_vadd_vv_i64m1 (a, b, vl);
+ return __riscv_vadd_vv_i64m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vadd_vv_i64m1' requires the zve64x, zve64f, zve64d or v ISA extension"
} */
}
/* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or
v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
index f0b72e5060b..bdd80cb731d 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
@@ -7,7 +7,7 @@ vfloat16m1_t
__attribute__((target("arch=+zve32f")))
test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f16m1 (a, b, vl);
+ return __riscv_vfadd_vv_f16m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f16m1' requires the zvfhmin or zvfh ISA extension" } */
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
index 9f22a182d4c..b78f9d792d8 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
@@ -7,7 +7,7 @@ vfloat64m1_t
__attribute__((target("arch=+zve32f")))
test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f64m1 (a, b, vl);
+ return __riscv_vfadd_vv_f64m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f64m1' requires the zve64d or v ISA extension" } */
}
/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
index 1006ad4af18..b6209bbd667 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
@@ -7,7 +7,7 @@ vfloat32m1_t
__attribute__((target("arch=+zve64x")))
test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f32m1 (a, b, vl);
+ return __riscv_vfadd_vv_f32m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f32m1' requires the zve32f, zve64f, zve64d or v ISA
extension" } */
}
/* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d
or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
index de36e4310b0..217bf37626c 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
@@ -7,7 +7,7 @@ vfloat16m1_t
__attribute__((target("arch=+zve64x")))
test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f16m1 (a, b, vl);
+ return __riscv_vfadd_vv_f16m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f16m1' requires the zvfhmin or zvfh ISA extension" } */
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
index f87f8c54c8d..39d687143ef 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
@@ -7,7 +7,7 @@ vfloat64m1_t
__attribute__((target("arch=+zve64x")))
test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f64m1 (a, b, vl);
+ return __riscv_vfadd_vv_f64m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f64m1' requires the zve64d or v ISA extension" } */
}
/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
index c5bc8511b67..54bb00505c2 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
@@ -7,7 +7,7 @@ vfloat64m1_t
__attribute__((target("arch=+zve64f")))
test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f64m1 (a, b, vl);
+ return __riscv_vfadd_vv_f64m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f64m1' requires the zve64d or v ISA extension" } */
}
/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
index 738d2e62748..5b5bff594a8 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
@@ -7,7 +7,7 @@ vfloat16m1_t
__attribute__((target("arch=+zve64f")))
test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f16m1 (a, b, vl);
+ return __riscv_vfadd_vv_f16m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f16m1' requires the zvfhmin or zvfh ISA extension" } */
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
index f82ad41cd50..32233876a2d 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
@@ -7,7 +7,7 @@ vfloat16m1_t
__attribute__((target("arch=+zve64d")))
test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
{
- return __riscv_vfadd_vv_f16m1 (a, b, vl);
+ return __riscv_vfadd_vv_f16m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vfadd_vv_f16m1' requires the zvfhmin or zvfh ISA extension" } */
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
index b9aceb83682..861d892b69a 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
@@ -7,7 +7,7 @@ vint32m1_t
__attribute__((target("arch=+zbb")))
test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
{
- return __riscv_vadd_vv_i32m1 (a, b, vl);
+ return __riscv_vadd_vv_i32m1 (a, b, vl); /* { dg-error "built-in function
'__riscv_vadd_vv_i32m1' requires the 'v' ISA extension" } */
}
/* { dg-error "return type 'vint32m1_t' requires the V ISA extension" "" {
target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
index d1dd811d14b..dd212d0fd6b 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
@@ -5,5 +5,5 @@
size_t test_1 (size_t vl)
{
- return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function
'__riscv_vsetvl_e8m4\(vl\)' requires the 'v' ISA extension} } */
+ return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function
'__riscv_vsetvl_e8m4' requires the 'v' ISA extension} } */
}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
index 9ff4c238124..83f040a82a7 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
@@ -19,5 +19,5 @@ test_2 ()
size_t
test_3 (size_t vl)
{
- return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function
'__riscv_vsetvl_e8m4\(vl\)' requires the 'v' ISA extension} } */
+ return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function
'__riscv_vsetvl_e8m4' requires the 'v' ISA extension} } */
}
--
2.55.0
