On Wed, Sep 23, 2026 at 05:27:59AM -0500, Vijay Shankar wrote: > Hello, > > Changes form v4: > * added AIX changes back > > Changes form v3: > * use TARGET_P10_FUSION instead of tuning conditions > * disable test for 32 bit > > Changes form v2: > * Removed AIX related changes > * update test case to check pattern directly > > Changes form v1: > * Cleaned up naming in rs6000.md > * Cleaned up guards to be on same line. > * Test case use \m...\M instead of relying on space > > Thank you, > Vijay. > > POWER10 has instruction fusion for addis+addi pairs. However, > the scheduler was breaking these pairs apart to optimize for > dependency chains, losing the fusion benefit. > > This patch implements "fake" instructions that represent both > instructions as a single pattern. This prevents the scheduler from > reordering them while still generating the correct two-instruction > sequence. > > Existing high/low patterns are guarded to > prevent conflicts with the new fusion patterns. > > Bootstrapped and tested on powerpc64le-linux-gnu with no regressions. > Bootstrapped and tested on powerpc64-linux-gnu with no regressions. > Bootstrapped and tested on powerpc-ibm-aix with no regressions. > > 2026-03-16 Vijay Shankar <[email protected]> > > gcc/ChangeLog: > PR target/108018 > * config/rs6000/rs6000.md (largetoc_high): Add guards. > (largetoc_high_aix<mode>): Likewise. > (largetoc_high_plus): Likewise. > (largetoc_high_plus_aix<mode>): Likewise. > (largetoc_low): Likewise. > (largetoc_low_aix<mode>): Likewise. > (largetocp10): New define_insn. > (largetocp10_aix<mode>): Likewise. > (largetocp10_plus): Likewise. > (largetocp10_plus_aix<mode>): Likewise. > (tocref<mode>): Add guards. > > gcc/testsuite/ChangeLog: > PR target/108018 > * gcc.target/powerpc/pr108018.c: New test.
This is ok for the master branch. Thanks for making the changes. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: [email protected]
