Ascalon retires at most one taken branch per cycle, so loops of
up to 8 instructions per iteration are limited by the branch. Let
the small loop unroller consider loops of up to 8 instructions,
and unroll them by up to 8.
While there were no measurable changes to SPEC CPU2017 (I tested
mcf, omnetpp and x264), there were improvements on microbenchmarks
comprising short loops (up to 8 instructions).
gcc/ChangeLog:
* config/riscv/riscv.cc (tt_ascalon_d8_tune_info): Set
small_loop_unroll_ninsns and small_loop_unroll_factor to 8.
---
gcc/config/riscv/riscv.cc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d75b890397..34e54b4eb81 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -840,6 +840,8 @@ static const struct riscv_tune_param
tt_ascalon_d8_tune_info = {
4, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
2, /* vec_reassoc_width. */
+ 8, /* small_loop_unroll_ninsns. */
+ 8, /* small_loop_unroll_factor. */
};
/* Costs to use when optimizing for size. */
--
2.34.1
