A number of Advanced SIMD patterns had C output blocks whose only job was
to convert an immediate lane number into architectural lane order before
printing it. The actual assembler template was otherwise fixed.
For example, a pattern could want to print a lane selected by operand 2,
but the printed lane depends on the number of lanes in the vector and on
endianness. Before this patch each pattern had to do that calculation
itself before returning the asm string.
This patch adds an internal named print operand for that operation:
%[ENDIAN_LANE<nunits>]2
The mode attribute supplies the lane count and operand 2 supplies the
lane. The AArch64 print hook then applies ENDIAN_LANE_N in one place and
prints the adjusted lane number.
That lets many patterns become plain output templates again, e.g.:
dup\t%0.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>]2]
The modifier is internal-only. It is just a machine-description helper for
printing the same lane numbers that the old C blocks printed.
Bootstrapped Regtested on aarch64-none-linux-gnu,
arm-none-linux-gnueabihf, x86_64-pc-linux-gnu
-m32, -m64 and no issues.
OK for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64.cc (A64_PRINT_endian_lane): New print code.
(operands_cache_initializer): Register ENDIAN_LANE* operands.
(aarch64_print_operand): Handle them.
* config/aarch64/aarch64-simd.md (@aarch64_dup_lane<mode>): Use
ENDIAN_LANE* print operands.
(@aarch64_dup_lane_<vswap_width_name><mode>): Likewise.
(aarch64_fcmla_laneq<rot>v4hf<vczle><vczbe>): Likewise.
(aarch64_<sur>dot_lane<vsi2qi><vczle><vczbe>): Likewise.
(aarch64_<sur>dot_laneq<vsi2qi><vczle><vczbe>): Likewise.
(sdot_lane<VF:isquadop><VDQSF:vsi2qi><vczle><vczbe>): Likewise.
(mul_lane<mode>3): Likewise.
(mul_laneq<mode>3): Likewise.
(*aarch64_mla_elt<mode><vczle><vczbe>): Likewise.
(*aarch64_mla_elt_<vswap_width_name><mode><vczle><vczbe>):
Likewise.
(*aarch64_mls_elt<mode><vczle><vczbe>): Likewise.
(*aarch64_mls_elt_<vswap_width_name><mode><vczle><vczbe>):
Likewise.
(aarch64_vec_<su>mult_lane<Qlane>): Likewise.
(aarch64_<su>mull_hi_lane<mode>_insn): Likewise.
(aarch64_<su>mull_hi_laneq<mode>_insn): Likewise.
(aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
(aarch64_<su>mlal_hi_lane<mode>_insn): Likewise.
(aarch64_<su>mlal_hi_laneq<mode>_insn): Likewise.
(aarch64_vec_<su>mlsl_lane<Qlane>): Likewise.
(aarch64_<su>mlsl_hi_lane<mode>_insn): Likewise.
(aarch64_<su>mlsl_hi_laneq<mode>_insn): Likewise.
(*aarch64_fma4_elt<mode><vczle><vczbe>): Likewise.
(*aarch64_fma4_elt_<vswap_width_name><mode><vczle><vczbe>):
Likewise.
(*aarch64_fma4_elt_to_64v2df): Likewise.
(*aarch64_fnma4_elt<mode><vczle><vczbe>): Likewise.
(*aarch64_fnma4_elt_<vswap_width_name><mode><vczle><vczbe>):
Likewise.
(*aarch64_fnma4_elt_to_64v2df): Likewise.
(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
(*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>): Likewise.
(@aarch64_get_lane<mode>): Likewise.
(*aarch64_mulx_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_mulx_elt<mode>): Likewise.
(*aarch64_vgetfmulx<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode><vczle><vczbe>): Likewise in all
definitions.
(aarch64_sq<r>dmulh_laneq<mode><vczle><vczbe>): Likewise in all
definitions.
(aarch64_sq<r>dmulh_lane<mode>): Likewise.
(aarch64_sq<r>dmulh_laneq<mode>): Likewise.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>):
Likewise in all definitions.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>):
Likewise in all definitions.
(aarch64_sqdmlal_lane<mode>): Likewise in all definitions.
(aarch64_sqdmlsl_lane<mode>): Likewise in all definitions.
(aarch64_sqdmlsl_laneq<mode>): Likewise in all definitions.
(aarch64_sqdmlal_laneq<mode>): Likewise in all definitions.
(aarch64_sqdmlsl2_lane<mode>_internal): Likewise.
(aarch64_sqdmlal2_lane<mode>_internal): Likewise.
(aarch64_sqdmlsl2_laneq<mode>_internal): Likewise.
(aarch64_sqdmlal2_laneq<mode>_internal): Likewise.
(aarch64_sqdmull_lane<mode>): Likewise in all definitions.
(aarch64_sqdmull_laneq<mode>): Likewise in all definitions.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
(aarch64_sqdmull2_laneq<mode>_internal): Likewise.
* config/aarch64/iterators.md (vcond_nunits): New mode attribute.
(vconq_nunits): Likewise.
(vswap_width_nunits): Likewise.
---
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index
98c2da034c55af8d56e63e3e9b8644d870b2d097..bf8e38a131ef6416b3623e2e66e2f4d4673e5152
100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -189,10 +189,7 @@ (define_insn "@aarch64_dup_lane<mode>"
(parallel [(match_operand:SI 2 "immediate_operand" "i")])
)))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "dup\\t%0.<Vtype>, %1.<Vetype>[%2]";
- }
+ "dup\\t%0.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_dup<q>")]
)
@@ -204,10 +201,7 @@ (define_insn "@aarch64_dup_lane_<vswap_width_name><mode>"
(parallel [(match_operand:SI 2 "immediate_operand" "i")])
)))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL
(operands[2]));
- return "dup\\t%0.<Vtype>, %1.<Vetype>[%2]";
- }
+ "dup\\t%0.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_dup<q>")]
)
@@ -636,10 +630,7 @@ (define_insn "aarch64_fcmla_laneq<rot>v4hf<vczle><vczbe>"
FCMLA)
(match_operand:V4HF 1 "register_operand" "0")))]
"TARGET_COMPLEX"
-{
- operands[4] = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));
- return "fcmla\t%0.4h, %2.4h, %3.h[%4], #<rot>";
-}
+ "fcmla\t%0.4h, %2.4h, %3.h[%[ENDIAN_LANE4:4]], #<rot>"
[(set_attr "type" "neon_fcmla")]
)
@@ -756,10 +747,7 @@ (define_insn "aarch64_<sur>dot_lane<vsi2qi><vczle><vczbe>"
DOTPROD)
(match_operand:VS 1 "register_operand" "0")))]
"TARGET_DOTPROD"
- {
- operands[4] = aarch64_endian_lane_rtx (V8QImode, INTVAL (operands[4]));
- return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]";
- }
+ "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%[ENDIAN_LANE8:4]]"
[(set_attr "type" "neon_dot<q>")]
)
@@ -772,10 +760,7 @@ (define_insn "aarch64_<sur>dot_laneq<vsi2qi><vczle><vczbe>"
DOTPROD)
(match_operand:VS 1 "register_operand" "0")))]
"TARGET_DOTPROD"
- {
- operands[4] = aarch64_endian_lane_rtx (V16QImode, INTVAL (operands[4]));
- return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]";
- }
+ "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%[ENDIAN_LANE16:4]]"
[(set_attr "type" "neon_dot<q>")]
)
@@ -822,10 +807,7 @@ (define_insn
"sdot_lane<VF:isquadop><VDQSF:vsi2qi><vczle><vczbe>"
UNSPEC_FDOT)
(match_operand:VDQSF 1 "register_operand" "0")))]
"TARGET_F16F32DOT"
-{
- operands[4] = aarch64_endian_lane_rtx (<VF:MODE>mode, INTVAL (operands[4]));
- return "fdot\t%0.<VDQSF:Vtype>, %2.<VDQSF:Vbfdottype>, %3.2h[%4]";
-}
+ "fdot\t%0.<VDQSF:Vtype>, %2.<VDQSF:Vbfdottype>,
%3.2h[%[ENDIAN_LANE<VF:nunits>:4]]"
[(set_attr "type" "neon_dot<VDQSF:q>")]
)
@@ -874,10 +856,7 @@ (define_insn "mul_lane<mode>3"
(parallel [(match_operand:SI 3 "immediate_operand" "i")])))
(match_operand:VMULD 1 "register_operand" "w")))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return "<f>mul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]";
- }
+ "<f>mul\\t%0.<Vtype>, %1.<Vtype>,
%2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
)
@@ -890,10 +869,7 @@ (define_insn "mul_laneq<mode>3"
(parallel [(match_operand:SI 3 "immediate_operand")])))
(match_operand:VMUL 1 "register_operand" "w")))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return "<f>mul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]";
- }
+ "<f>mul\\t%0.<Vtype>, %1.<Vtype>,
%2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
)
@@ -1981,10 +1957,7 @@ (define_insn "*aarch64_mla_elt<mode><vczle><vczbe>"
(match_operand:VDQHS 3 "register_operand" "w"))
(match_operand:VDQHS 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -1999,10 +1972,7 @@ (define_insn
"*aarch64_mla_elt_<vswap_width_name><mode><vczle><vczbe>"
(match_operand:VDQHS 3 "register_operand" "w"))
(match_operand:VDQHS 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL
(operands[2]));
- return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "mla\t%0.<Vtype>, %3.<Vtype>,
%1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -2040,10 +2010,7 @@ (define_insn "*aarch64_mls_elt<mode><vczle><vczbe>"
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -2058,10 +2025,7 @@ (define_insn
"*aarch64_mls_elt_<vswap_width_name><mode><vczle><vczbe>"
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL
(operands[2]));
- return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "mls\t%0.<Vtype>, %3.<Vtype>,
%1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -2636,10 +2600,7 @@ (define_insn "aarch64_vec_<su>mult_lane<Qlane>"
(match_operand:VDQHS 2 "register_operand" "<vwx>")
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))))))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[3]));
- return "<su>mull\\t%0.<Vwtype>, %1.<Vcondtype>, %2.<Vetype>[%3]";
- }
+ "<su>mull\\t%0.<Vwtype>, %1.<Vcondtype>,
%2.<Vetype>[%[ENDIAN_LANE<nunits>:3]]"
[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
)
@@ -2656,10 +2617,7 @@ (define_insn "aarch64_<su>mull_hi_lane<mode>_insn"
(match_operand:<VCOND> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %3.<Vetype>[%4]";
- }
+ "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
)
@@ -2690,10 +2648,7 @@ (define_insn "aarch64_<su>mull_hi_laneq<mode>_insn"
(match_operand:<VCONQ> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %3.<Vetype>[%4]";
- }
+ "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>,
%3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
)
@@ -2766,10 +2721,7 @@ (define_insn "aarch64_vec_<su>mlal_lane<Qlane>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")])))))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4]));
- return "<su>mlal\\t%0.<Vwtype>, %2.<Vcondtype>, %3.<Vetype>[%4]";
- }
+ "<su>mlal\\t%0.<Vwtype>, %2.<Vcondtype>,
%3.<Vetype>[%[ENDIAN_LANE<nunits>:4]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2788,10 +2740,7 @@ (define_insn "aarch64_<su>mlal_hi_lane<mode>_insn"
(parallel [(match_operand:SI 5 "immediate_operand" "i")])))))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[5] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[5]));
- return "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]";
- }
+ "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>,
%4.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:5]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2825,10 +2774,7 @@ (define_insn "aarch64_<su>mlal_hi_laneq<mode>_insn"
(parallel [(match_operand:SI 5 "immediate_operand" "i")])))))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[5] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[5]));
- return "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]";
- }
+ "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>,
%4.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:5]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2860,10 +2806,7 @@ (define_insn "aarch64_vec_<su>mlsl_lane<Qlane>"
(match_operand:VDQHS 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")])))))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4]));
- return "<su>mlsl\\t%0.<Vwtype>, %2.<Vcondtype>, %3.<Vetype>[%4]";
- }
+ "<su>mlsl\\t%0.<Vwtype>, %2.<Vcondtype>,
%3.<Vetype>[%[ENDIAN_LANE<nunits>:4]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2883,10 +2826,7 @@ (define_insn "aarch64_<su>mlsl_hi_lane<mode>_insn"
(parallel [(match_operand:SI 5 "immediate_operand" "i")]))))
)))]
"TARGET_SIMD"
- {
- operands[5] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[5]));
- return "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]";
- }
+ "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>,
%4.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:5]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2921,10 +2861,7 @@ (define_insn "aarch64_<su>mlsl_hi_laneq<mode>_insn"
(parallel [(match_operand:SI 5 "immediate_operand" "i")]))))
)))]
"TARGET_SIMD"
- {
- operands[5] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[5]));
- return "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]";
- }
+ "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>,
%4.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:5]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -3207,10 +3144,7 @@ (define_insn "*aarch64_fma4_elt<mode><vczle><vczbe>"
(match_operand:VDQF 3 "register_operand" "w")
(match_operand:VDQF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -3224,10 +3158,7 @@ (define_insn
"*aarch64_fma4_elt_<vswap_width_name><mode><vczle><vczbe>"
(match_operand:VDQSF 3 "register_operand" "w")
(match_operand:VDQSF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL
(operands[2]));
- return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "fmla\\t%0.<Vtype>, %3.<Vtype>,
%1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -3252,10 +3183,7 @@ (define_insn "*aarch64_fma4_elt_to_64v2df"
(match_operand:DF 3 "register_operand" "w")
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
- return "fmla\\t%0.2d, %3.2d, %1.d[%2]";
- }
+ "fmla\\t%0.2d, %3.2d, %1.d[%[ENDIAN_LANE2:2]]"
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
@@ -3281,10 +3209,7 @@ (define_insn "*aarch64_fnma4_elt<mode><vczle><vczbe>"
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -3299,10 +3224,7 @@ (define_insn
"*aarch64_fnma4_elt_<vswap_width_name><mode><vczle><vczbe>"
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQSF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL
(operands[2]));
- return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "fmls\\t%0.<Vtype>, %3.<Vtype>,
%1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -3329,10 +3251,7 @@ (define_insn "*aarch64_fnma4_elt_to_64v2df"
(match_operand:DF 3 "register_operand" "w"))
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
- return "fmls\\t%0.2d, %3.2d, %1.d[%2]";
- }
+ "fmls\\t%0.2d, %3.2d, %1.d[%[ENDIAN_LANE2:2]]"
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
@@ -4881,11 +4800,7 @@ (define_insn
"*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>"
(match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
- INTVAL (operands[2]));
- return "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]";
- }
+ "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%[ENDIAN_LANE<VDQQH:nunits>:2]]"
[(set_attr "type" "neon_to_gp<VDQQH:q>")]
)
@@ -4896,11 +4811,7 @@ (define_insn
"*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>"
(match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
- INTVAL (operands[2]));
- return "umov\\t%w0, %1.<VDQQH:Vetype>[%2]";
- }
+ "umov\\t%w0, %1.<VDQQH:Vetype>[%[ENDIAN_LANE<VDQQH:nunits>:2]]"
[(set_attr "type" "neon_to_gp<VDQQH:q>")]
)
@@ -4910,24 +4821,15 @@ (define_insn
"*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>"
;; Extracting lane zero is split into a simple move when it is between SIMD
;; registers or a store.
(define_insn_and_split "@aarch64_get_lane<mode>"
- [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=?r, w,
Utv")
+ [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand")
(vec_select:<VEL>
- (match_operand:VALL_F16 1 "register_operand" "w, w, w")
- (parallel [(match_operand:SI 2 "immediate_operand" "i, i, i")])))]
+ (match_operand:VALL_F16 1 "register_operand")
+ (parallel [(match_operand:SI 2 "immediate_operand")])))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- switch (which_alternative)
- {
- case 0:
- return "umov\\t%<vwcore>0, %1.<Vetype>[%2]";
- case 1:
- return "dup\\t%<Vetype>0, %1.<Vetype>[%2]";
- case 2:
- return "st1\\t{%1.<Vetype>}[%2], %0";
- default:
- gcc_unreachable ();
- }
+ {@ [cons: =0 , 1 , 2 ; attrs: type]
+ [ ?r , w , i ; neon_to_gp<q> ] umov\t%<vwcore>0,
%1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]
+ [ w , w , i ; neon_dup<q> ] dup\t%<Vetype>0,
%1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]
+ [ Utv , w , i ; neon_store1_one_lane<q> ]
st1\t{%1.<Vetype>}[%[ENDIAN_LANE<nunits>:2]], %0
}
"&& reload_completed
&& ENDIAN_LANE_N (<nunits>, INTVAL (operands[2])) == 0"
@@ -4935,7 +4837,6 @@ (define_insn_and_split "@aarch64_get_lane<mode>"
{
operands[1] = aarch64_replace_reg_mode (operands[1], <VEL>mode);
}
- [(set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")]
)
(define_insn "*aarch64_get_high<mode>"
@@ -5931,10 +5832,7 @@ (define_insn "*aarch64_mulx_elt_<vswap_width_name><mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")])))]
UNSPEC_FMULX))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL
(operands[3]));
- return "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>,
%2.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:3]]"
[(set_attr "type" "neon_fp_mul_<Vetype>_scalar<q>")]
)
@@ -5950,10 +5848,7 @@ (define_insn "*aarch64_mulx_elt<mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")])))]
UNSPEC_FMULX))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[3]));
- return "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<nunits>:3]]"
[(set_attr "type" "neon_fp_mul_<Vetype><q>")]
)
@@ -5984,10 +5879,7 @@ (define_insn "*aarch64_vgetfmulx<mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
UNSPEC_FMULX))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[3]));
- return "fmulx\t%<Vetype>0, %<Vetype>1, %2.<Vetype>[%3]";
- }
+ "fmulx\t%<Vetype>0, %<Vetype>1, %2.<Vetype>[%[ENDIAN_LANE<nunits>:3]]"
[(set_attr "type" "fmul<Vetype>")]
)
;; <su>q<addsub>
@@ -6403,9 +6295,7 @@ (define_insn "aarch64_sq<r>dmulh_lane<mode><vczle><vczbe>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
VQDMULH))]
"TARGET_SIMD"
- "*
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
+ "sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>,
%2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -6418,9 +6308,7 @@ (define_insn
"aarch64_sq<r>dmulh_laneq<mode><vczle><vczbe>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
VQDMULH))]
"TARGET_SIMD"
- "*
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
+ "sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>,
%2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -6433,9 +6321,7 @@ (define_insn "aarch64_sq<r>dmulh_lane<mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
VQDMULH))]
"TARGET_SIMD"
- "*
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
+ "sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -6448,9 +6334,7 @@ (define_insn "aarch64_sq<r>dmulh_laneq<mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
VQDMULH))]
"TARGET_SIMD"
- "*
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
+ "sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -6480,11 +6364,7 @@ (define_insn
"aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%4]";
- }
+ "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6498,11 +6378,7 @@ (define_insn
"aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2, %3.<Vetype>[%4]";
- }
+ "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6518,11 +6394,7 @@ (define_insn
"aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%4]";
- }
+ "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>,
%3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6536,11 +6408,7 @@ (define_insn
"aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2, %3.<v>[%4]";
- }
+ "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2,
%3.<v>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6596,11 +6464,7 @@ (define_insn "aarch64_sqdmlal_lane<mode>"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6620,11 +6484,7 @@ (define_insn "aarch64_sqdmlsl_lane<mode>"
))
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6645,11 +6505,7 @@ (define_insn "aarch64_sqdmlsl_laneq<mode>"
))
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6669,11 +6525,7 @@ (define_insn "aarch64_sqdmlal_laneq<mode>"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6693,11 +6545,7 @@ (define_insn "aarch64_sqdmlal_lane<mode>"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6716,11 +6564,7 @@ (define_insn "aarch64_sqdmlsl_lane<mode>"
)
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6740,11 +6584,7 @@ (define_insn "aarch64_sqdmlal_laneq<mode>"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6763,11 +6603,7 @@ (define_insn "aarch64_sqdmlsl_laneq<mode>"
)
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6886,11 +6722,7 @@ (define_insn "aarch64_sqdmlsl2_lane<mode>_internal"
))))
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6912,11 +6744,7 @@ (define_insn "aarch64_sqdmlal2_lane<mode>_internal"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6938,11 +6766,7 @@ (define_insn "aarch64_sqdmlsl2_laneq<mode>_internal"
))))
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6964,11 +6788,7 @@ (define_insn "aarch64_sqdmlal2_laneq<mode>_internal"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>,
%3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -7092,10 +6912,7 @@ (define_insn "aarch64_sqdmull_lane<mode>"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>,
%2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7113,10 +6930,7 @@ (define_insn "aarch64_sqdmull_laneq<mode>"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>,
%2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7133,10 +6947,7 @@ (define_insn "aarch64_sqdmull_lane<mode>"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>,
%2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7153,10 +6964,7 @@ (define_insn "aarch64_sqdmull_laneq<mode>"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>,
%2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7229,10 +7037,7 @@ (define_insn "aarch64_sqdmull2_lane<mode>_internal"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>,
%2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7252,10 +7057,7 @@ (define_insn "aarch64_sqdmull2_laneq<mode>_internal"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>,
%2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index
70d739f9b9ac56dec02de4cde5ea2a87f75f64af..48c1310a586e27c8406a826847685af43a315ef0
100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -13263,6 +13263,8 @@ typedef enum aarch64_print_operands {
A64_PRINT_addr_ldp_stp_np,
/* Output address of a typical LDP or STP. */
A64_PRINT_addr_ldp_stp,
+ /* Print an Advanced SIMD lane number in architectural lane order. */
+ A64_PRINT_endian_lane,
/* Print the final element offset for an SME vector group. */
A64_PRINT_sme_vg_end,
/* Print the inclusive end of an SME slice range. */
@@ -13329,6 +13331,11 @@ struct operands_cache_initializer
DEF_PUBLIC_OPERAND (X, A64_PRINT_bottom_16bits);
DEF_PUBLIC_OPERAND (y, A64_PRINT_addr_ldp_stp_np);
DEF_PUBLIC_OPERAND (z, A64_PRINT_addr_ldp_stp);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE1, A64_PRINT_endian_lane, 1);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE2, A64_PRINT_endian_lane, 2);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE4, A64_PRINT_endian_lane, 4);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE8, A64_PRINT_endian_lane, 8);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE16, A64_PRINT_endian_lane, 16);
DEF_PRIVATE_OPERAND (SME_VG_END, A64_PRINT_sme_vg_end);
DEF_PRIVATE_OPERAND_EXT (SME_RANGE_END1, A64_PRINT_sme_range_end, 1);
DEF_PRIVATE_OPERAND_EXT (SME_RANGE_END3, A64_PRINT_sme_range_end, 3);
@@ -13895,6 +13902,21 @@ aarch64_print_operand (FILE *f, rtx x, int code)
}
break;
+ case A64_PRINT_endian_lane:
+ {
+ uintptr_t nunits = (uintptr_t) print_info.extra;
+
+ if (nunits == 0 || !CONST_INT_P (x))
+ {
+ output_operand_lossage ("invalid operand for '%%%s'",
+ token.c_str ());
+ return;
+ }
+
+ asm_fprintf (f, "%wd", ENDIAN_LANE_N (nunits, INTVAL (x)));
+ }
+ break;
+
case A64_PRINT_sme_vg_end:
if (!REG_P (x) || !FP_REGNUM_P (REGNO (x)))
{
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index
568786e37149a1292a7a0ed391f88fde51e23a62..ca83b7ca08be4934aaa0624d18bd6c67894ab2fa
100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2075,6 +2075,21 @@ (define_mode_attr vcond [(HI "v4hi") (SI "v2si")
(V2SF "v2sf") (V4SF "v2sf")
(V2DF "df")])
+;; Number of units in VCOND.
+(define_mode_attr vcond_nunits [(HI "4") (SI "2")
+ (V2HI "4")
+ (V4HI "4") (V8HI "4")
+ (V2SI "2") (V4SI "2")
+ (QI "8") (V2QI "8")
+ (V4QI "8")
+ (DI "1") (V2DI "1")
+ (HF "4") (V2HF "4")
+ (V4HF "4") (V8HF "4")
+ (BF "4") (V2BF "4")
+ (SF "2")
+ (V2SF "2") (V4SF "2")
+ (V2DF "1")])
+
;; 128-bit container modes the inner or scalar source mode.
(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
(V4QI "V16QI") (V2QI "V16QI")
@@ -2107,6 +2122,22 @@ (define_mode_attr vconq [(V8QI "v16qi") (V16QI "v16qi")
(HI "v8hi") (QI "v16qi")
(SF "v4sf") (DF "v2df")])
+;; Number of units in VCONQ.
+(define_mode_attr vconq_nunits [(V8QI "16") (V16QI "16")
+ (V4QI "16") (V2QI "16")
+ (V4HI "8") (V8HI "8")
+ (V2HI "8")
+ (V2SI "4") (V4SI "4")
+ (DI "2") (V2DI "2")
+ (V4HF "8") (V8HF "8")
+ (V2HF "8") (HF "8")
+ (V4BF "8") (V8BF "8")
+ (V2BF "8") (BF "8")
+ (V2SF "4") (V4SF "4")
+ (V2DF "2") (SI "4")
+ (HI "8") (QI "16")
+ (SF "4") (DF "2")])
+
;; SVE container modes for duplication into a full SVE register.
(define_mode_attr VCONSV [(V8QI "VNx16QI") (V4QI "VNx16QI")
(V2QI "VNx16QI") (QI "VNx16QI")
@@ -2688,6 +2719,16 @@ (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI
"V8QI")
(V4HF "V8HF") (V8HF "V4HF")
(DF "V2DF") (V2DF "DF")])
+;; Number of units in VSWAP_WIDTH.
+(define_mode_attr vswap_width_nunits [(V8QI "16") (V16QI "8")
+ (V4HI "8") (V8HI "4")
+ (V8BF "4") (V4BF "8")
+ (V2SI "4") (V4SI "2")
+ (DI "2") (V2DI "1")
+ (V2SF "4") (V4SF "2")
+ (V4HF "8") (V8HF "4")
+ (DF "2") (V2DF "1")])
+
(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
(V4HI "to_128") (V8HI "to_64")
(V2SI "to_128") (V4SI "to_64")
--
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 98c2da034c55af8d56e63e3e9b8644d870b2d097..bf8e38a131ef6416b3623e2e66e2f4d4673e5152 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -189,10 +189,7 @@ (define_insn "@aarch64_dup_lane<mode>"
(parallel [(match_operand:SI 2 "immediate_operand" "i")])
)))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "dup\\t%0.<Vtype>, %1.<Vetype>[%2]";
- }
+ "dup\\t%0.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_dup<q>")]
)
@@ -204,10 +201,7 @@ (define_insn "@aarch64_dup_lane_<vswap_width_name><mode>"
(parallel [(match_operand:SI 2 "immediate_operand" "i")])
)))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "dup\\t%0.<Vtype>, %1.<Vetype>[%2]";
- }
+ "dup\\t%0.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_dup<q>")]
)
@@ -636,10 +630,7 @@ (define_insn "aarch64_fcmla_laneq<rot>v4hf<vczle><vczbe>"
FCMLA)
(match_operand:V4HF 1 "register_operand" "0")))]
"TARGET_COMPLEX"
-{
- operands[4] = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));
- return "fcmla\t%0.4h, %2.4h, %3.h[%4], #<rot>";
-}
+ "fcmla\t%0.4h, %2.4h, %3.h[%[ENDIAN_LANE4:4]], #<rot>"
[(set_attr "type" "neon_fcmla")]
)
@@ -756,10 +747,7 @@ (define_insn "aarch64_<sur>dot_lane<vsi2qi><vczle><vczbe>"
DOTPROD)
(match_operand:VS 1 "register_operand" "0")))]
"TARGET_DOTPROD"
- {
- operands[4] = aarch64_endian_lane_rtx (V8QImode, INTVAL (operands[4]));
- return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]";
- }
+ "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%[ENDIAN_LANE8:4]]"
[(set_attr "type" "neon_dot<q>")]
)
@@ -772,10 +760,7 @@ (define_insn "aarch64_<sur>dot_laneq<vsi2qi><vczle><vczbe>"
DOTPROD)
(match_operand:VS 1 "register_operand" "0")))]
"TARGET_DOTPROD"
- {
- operands[4] = aarch64_endian_lane_rtx (V16QImode, INTVAL (operands[4]));
- return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]";
- }
+ "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%[ENDIAN_LANE16:4]]"
[(set_attr "type" "neon_dot<q>")]
)
@@ -822,10 +807,7 @@ (define_insn "sdot_lane<VF:isquadop><VDQSF:vsi2qi><vczle><vczbe>"
UNSPEC_FDOT)
(match_operand:VDQSF 1 "register_operand" "0")))]
"TARGET_F16F32DOT"
-{
- operands[4] = aarch64_endian_lane_rtx (<VF:MODE>mode, INTVAL (operands[4]));
- return "fdot\t%0.<VDQSF:Vtype>, %2.<VDQSF:Vbfdottype>, %3.2h[%4]";
-}
+ "fdot\t%0.<VDQSF:Vtype>, %2.<VDQSF:Vbfdottype>, %3.2h[%[ENDIAN_LANE<VF:nunits>:4]]"
[(set_attr "type" "neon_dot<VDQSF:q>")]
)
@@ -874,10 +856,7 @@ (define_insn "mul_lane<mode>3"
(parallel [(match_operand:SI 3 "immediate_operand" "i")])))
(match_operand:VMULD 1 "register_operand" "w")))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return "<f>mul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]";
- }
+ "<f>mul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
)
@@ -890,10 +869,7 @@ (define_insn "mul_laneq<mode>3"
(parallel [(match_operand:SI 3 "immediate_operand")])))
(match_operand:VMUL 1 "register_operand" "w")))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return "<f>mul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]";
- }
+ "<f>mul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
)
@@ -1981,10 +1957,7 @@ (define_insn "*aarch64_mla_elt<mode><vczle><vczbe>"
(match_operand:VDQHS 3 "register_operand" "w"))
(match_operand:VDQHS 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -1999,10 +1972,7 @@ (define_insn "*aarch64_mla_elt_<vswap_width_name><mode><vczle><vczbe>"
(match_operand:VDQHS 3 "register_operand" "w"))
(match_operand:VDQHS 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -2040,10 +2010,7 @@ (define_insn "*aarch64_mls_elt<mode><vczle><vczbe>"
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -2058,10 +2025,7 @@ (define_insn "*aarch64_mls_elt_<vswap_width_name><mode><vczle><vczbe>"
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -2636,10 +2600,7 @@ (define_insn "aarch64_vec_<su>mult_lane<Qlane>"
(match_operand:VDQHS 2 "register_operand" "<vwx>")
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))))))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[3]));
- return "<su>mull\\t%0.<Vwtype>, %1.<Vcondtype>, %2.<Vetype>[%3]";
- }
+ "<su>mull\\t%0.<Vwtype>, %1.<Vcondtype>, %2.<Vetype>[%[ENDIAN_LANE<nunits>:3]]"
[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
)
@@ -2656,10 +2617,7 @@ (define_insn "aarch64_<su>mull_hi_lane<mode>_insn"
(match_operand:<VCOND> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %3.<Vetype>[%4]";
- }
+ "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
)
@@ -2690,10 +2648,7 @@ (define_insn "aarch64_<su>mull_hi_laneq<mode>_insn"
(match_operand:<VCONQ> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %3.<Vetype>[%4]";
- }
+ "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
)
@@ -2766,10 +2721,7 @@ (define_insn "aarch64_vec_<su>mlal_lane<Qlane>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")])))))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4]));
- return "<su>mlal\\t%0.<Vwtype>, %2.<Vcondtype>, %3.<Vetype>[%4]";
- }
+ "<su>mlal\\t%0.<Vwtype>, %2.<Vcondtype>, %3.<Vetype>[%[ENDIAN_LANE<nunits>:4]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2788,10 +2740,7 @@ (define_insn "aarch64_<su>mlal_hi_lane<mode>_insn"
(parallel [(match_operand:SI 5 "immediate_operand" "i")])))))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[5] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[5]));
- return "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]";
- }
+ "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:5]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2825,10 +2774,7 @@ (define_insn "aarch64_<su>mlal_hi_laneq<mode>_insn"
(parallel [(match_operand:SI 5 "immediate_operand" "i")])))))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[5] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[5]));
- return "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]";
- }
+ "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:5]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2860,10 +2806,7 @@ (define_insn "aarch64_vec_<su>mlsl_lane<Qlane>"
(match_operand:VDQHS 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")])))))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4]));
- return "<su>mlsl\\t%0.<Vwtype>, %2.<Vcondtype>, %3.<Vetype>[%4]";
- }
+ "<su>mlsl\\t%0.<Vwtype>, %2.<Vcondtype>, %3.<Vetype>[%[ENDIAN_LANE<nunits>:4]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2883,10 +2826,7 @@ (define_insn "aarch64_<su>mlsl_hi_lane<mode>_insn"
(parallel [(match_operand:SI 5 "immediate_operand" "i")]))))
)))]
"TARGET_SIMD"
- {
- operands[5] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[5]));
- return "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]";
- }
+ "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:5]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -2921,10 +2861,7 @@ (define_insn "aarch64_<su>mlsl_hi_laneq<mode>_insn"
(parallel [(match_operand:SI 5 "immediate_operand" "i")]))))
)))]
"TARGET_SIMD"
- {
- operands[5] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[5]));
- return "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]";
- }
+ "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:5]]"
[(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
)
@@ -3207,10 +3144,7 @@ (define_insn "*aarch64_fma4_elt<mode><vczle><vczbe>"
(match_operand:VDQF 3 "register_operand" "w")
(match_operand:VDQF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -3224,10 +3158,7 @@ (define_insn "*aarch64_fma4_elt_<vswap_width_name><mode><vczle><vczbe>"
(match_operand:VDQSF 3 "register_operand" "w")
(match_operand:VDQSF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -3252,10 +3183,7 @@ (define_insn "*aarch64_fma4_elt_to_64v2df"
(match_operand:DF 3 "register_operand" "w")
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
- return "fmla\\t%0.2d, %3.2d, %1.d[%2]";
- }
+ "fmla\\t%0.2d, %3.2d, %1.d[%[ENDIAN_LANE2:2]]"
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
@@ -3281,10 +3209,7 @@ (define_insn "*aarch64_fnma4_elt<mode><vczle><vczbe>"
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]"
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -3299,10 +3224,7 @@ (define_insn "*aarch64_fnma4_elt_<vswap_width_name><mode><vczle><vczbe>"
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQSF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
- }
+ "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:2]]"
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -3329,10 +3251,7 @@ (define_insn "*aarch64_fnma4_elt_to_64v2df"
(match_operand:DF 3 "register_operand" "w"))
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
- return "fmls\\t%0.2d, %3.2d, %1.d[%2]";
- }
+ "fmls\\t%0.2d, %3.2d, %1.d[%[ENDIAN_LANE2:2]]"
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
@@ -4881,11 +4800,7 @@ (define_insn "*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>"
(match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
- INTVAL (operands[2]));
- return "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]";
- }
+ "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%[ENDIAN_LANE<VDQQH:nunits>:2]]"
[(set_attr "type" "neon_to_gp<VDQQH:q>")]
)
@@ -4896,11 +4811,7 @@ (define_insn "*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>"
(match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
- INTVAL (operands[2]));
- return "umov\\t%w0, %1.<VDQQH:Vetype>[%2]";
- }
+ "umov\\t%w0, %1.<VDQQH:Vetype>[%[ENDIAN_LANE<VDQQH:nunits>:2]]"
[(set_attr "type" "neon_to_gp<VDQQH:q>")]
)
@@ -4910,24 +4821,15 @@ (define_insn "*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>"
;; Extracting lane zero is split into a simple move when it is between SIMD
;; registers or a store.
(define_insn_and_split "@aarch64_get_lane<mode>"
- [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=?r, w, Utv")
+ [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand")
(vec_select:<VEL>
- (match_operand:VALL_F16 1 "register_operand" "w, w, w")
- (parallel [(match_operand:SI 2 "immediate_operand" "i, i, i")])))]
+ (match_operand:VALL_F16 1 "register_operand")
+ (parallel [(match_operand:SI 2 "immediate_operand")])))]
"TARGET_SIMD"
- {
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- switch (which_alternative)
- {
- case 0:
- return "umov\\t%<vwcore>0, %1.<Vetype>[%2]";
- case 1:
- return "dup\\t%<Vetype>0, %1.<Vetype>[%2]";
- case 2:
- return "st1\\t{%1.<Vetype>}[%2], %0";
- default:
- gcc_unreachable ();
- }
+ {@ [cons: =0 , 1 , 2 ; attrs: type]
+ [ ?r , w , i ; neon_to_gp<q> ] umov\t%<vwcore>0, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]
+ [ w , w , i ; neon_dup<q> ] dup\t%<Vetype>0, %1.<Vetype>[%[ENDIAN_LANE<nunits>:2]]
+ [ Utv , w , i ; neon_store1_one_lane<q> ] st1\t{%1.<Vetype>}[%[ENDIAN_LANE<nunits>:2]], %0
}
"&& reload_completed
&& ENDIAN_LANE_N (<nunits>, INTVAL (operands[2])) == 0"
@@ -4935,7 +4837,6 @@ (define_insn_and_split "@aarch64_get_lane<mode>"
{
operands[1] = aarch64_replace_reg_mode (operands[1], <VEL>mode);
}
- [(set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")]
)
(define_insn "*aarch64_get_high<mode>"
@@ -5931,10 +5832,7 @@ (define_insn "*aarch64_mulx_elt_<vswap_width_name><mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")])))]
UNSPEC_FMULX))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[3]));
- return "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<vswap_width_nunits>:3]]"
[(set_attr "type" "neon_fp_mul_<Vetype>_scalar<q>")]
)
@@ -5950,10 +5848,7 @@ (define_insn "*aarch64_mulx_elt<mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")])))]
UNSPEC_FMULX))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[3]));
- return "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<nunits>:3]]"
[(set_attr "type" "neon_fp_mul_<Vetype><q>")]
)
@@ -5984,10 +5879,7 @@ (define_insn "*aarch64_vgetfmulx<mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
UNSPEC_FMULX))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[3]));
- return "fmulx\t%<Vetype>0, %<Vetype>1, %2.<Vetype>[%3]";
- }
+ "fmulx\t%<Vetype>0, %<Vetype>1, %2.<Vetype>[%[ENDIAN_LANE<nunits>:3]]"
[(set_attr "type" "fmul<Vetype>")]
)
;; <su>q<addsub>
@@ -6403,9 +6295,7 @@ (define_insn "aarch64_sq<r>dmulh_lane<mode><vczle><vczbe>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
VQDMULH))]
"TARGET_SIMD"
- "*
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
+ "sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -6418,9 +6308,7 @@ (define_insn "aarch64_sq<r>dmulh_laneq<mode><vczle><vczbe>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
VQDMULH))]
"TARGET_SIMD"
- "*
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
+ "sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -6433,9 +6321,7 @@ (define_insn "aarch64_sq<r>dmulh_lane<mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
VQDMULH))]
"TARGET_SIMD"
- "*
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
+ "sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -6448,9 +6334,7 @@ (define_insn "aarch64_sq<r>dmulh_laneq<mode>"
(parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
VQDMULH))]
"TARGET_SIMD"
- "*
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
+ "sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -6480,11 +6364,7 @@ (define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%4]";
- }
+ "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6498,11 +6378,7 @@ (define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2, %3.<Vetype>[%4]";
- }
+ "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6518,11 +6394,7 @@ (define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%4]";
- }
+ "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6536,11 +6408,7 @@ (define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>"
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2, %3.<v>[%4]";
- }
+ "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2, %3.<v>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6596,11 +6464,7 @@ (define_insn "aarch64_sqdmlal_lane<mode>"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6620,11 +6484,7 @@ (define_insn "aarch64_sqdmlsl_lane<mode>"
))
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6645,11 +6505,7 @@ (define_insn "aarch64_sqdmlsl_laneq<mode>"
))
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6669,11 +6525,7 @@ (define_insn "aarch64_sqdmlal_laneq<mode>"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6693,11 +6545,7 @@ (define_insn "aarch64_sqdmlal_lane<mode>"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6716,11 +6564,7 @@ (define_insn "aarch64_sqdmlsl_lane<mode>"
)
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6740,11 +6584,7 @@ (define_insn "aarch64_sqdmlal_laneq<mode>"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6763,11 +6603,7 @@ (define_insn "aarch64_sqdmlsl_laneq<mode>"
)
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6886,11 +6722,7 @@ (define_insn "aarch64_sqdmlsl2_lane<mode>_internal"
))))
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6912,11 +6744,7 @@ (define_insn "aarch64_sqdmlal2_lane<mode>_internal"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
- return
- "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6938,11 +6766,7 @@ (define_insn "aarch64_sqdmlsl2_laneq<mode>_internal"
))))
(const_int 1))))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -6964,11 +6788,7 @@ (define_insn "aarch64_sqdmlal2_laneq<mode>_internal"
(const_int 1))
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- {
- operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
- return
- "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
- }
+ "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:4]]"
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -7092,10 +6912,7 @@ (define_insn "aarch64_sqdmull_lane<mode>"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7113,10 +6930,7 @@ (define_insn "aarch64_sqdmull_laneq<mode>"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7133,10 +6947,7 @@ (define_insn "aarch64_sqdmull_lane<mode>"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7153,10 +6964,7 @@ (define_insn "aarch64_sqdmull_laneq<mode>"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7229,10 +7037,7 @@ (define_insn "aarch64_sqdmull2_lane<mode>_internal"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[3]));
- return "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<vcond_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -7252,10 +7057,7 @@ (define_insn "aarch64_sqdmull2_laneq<mode>_internal"
))
(const_int 1)))]
"TARGET_SIMD"
- {
- operands[3] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[3]));
- return "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
- }
+ "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%[ENDIAN_LANE<vconq_nunits>:3]]"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 70d739f9b9ac56dec02de4cde5ea2a87f75f64af..48c1310a586e27c8406a826847685af43a315ef0 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -13263,6 +13263,8 @@ typedef enum aarch64_print_operands {
A64_PRINT_addr_ldp_stp_np,
/* Output address of a typical LDP or STP. */
A64_PRINT_addr_ldp_stp,
+ /* Print an Advanced SIMD lane number in architectural lane order. */
+ A64_PRINT_endian_lane,
/* Print the final element offset for an SME vector group. */
A64_PRINT_sme_vg_end,
/* Print the inclusive end of an SME slice range. */
@@ -13329,6 +13331,11 @@ struct operands_cache_initializer
DEF_PUBLIC_OPERAND (X, A64_PRINT_bottom_16bits);
DEF_PUBLIC_OPERAND (y, A64_PRINT_addr_ldp_stp_np);
DEF_PUBLIC_OPERAND (z, A64_PRINT_addr_ldp_stp);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE1, A64_PRINT_endian_lane, 1);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE2, A64_PRINT_endian_lane, 2);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE4, A64_PRINT_endian_lane, 4);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE8, A64_PRINT_endian_lane, 8);
+ DEF_PRIVATE_OPERAND_EXT (ENDIAN_LANE16, A64_PRINT_endian_lane, 16);
DEF_PRIVATE_OPERAND (SME_VG_END, A64_PRINT_sme_vg_end);
DEF_PRIVATE_OPERAND_EXT (SME_RANGE_END1, A64_PRINT_sme_range_end, 1);
DEF_PRIVATE_OPERAND_EXT (SME_RANGE_END3, A64_PRINT_sme_range_end, 3);
@@ -13895,6 +13902,21 @@ aarch64_print_operand (FILE *f, rtx x, int code)
}
break;
+ case A64_PRINT_endian_lane:
+ {
+ uintptr_t nunits = (uintptr_t) print_info.extra;
+
+ if (nunits == 0 || !CONST_INT_P (x))
+ {
+ output_operand_lossage ("invalid operand for '%%%s'",
+ token.c_str ());
+ return;
+ }
+
+ asm_fprintf (f, "%wd", ENDIAN_LANE_N (nunits, INTVAL (x)));
+ }
+ break;
+
case A64_PRINT_sme_vg_end:
if (!REG_P (x) || !FP_REGNUM_P (REGNO (x)))
{
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 568786e37149a1292a7a0ed391f88fde51e23a62..ca83b7ca08be4934aaa0624d18bd6c67894ab2fa 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2075,6 +2075,21 @@ (define_mode_attr vcond [(HI "v4hi") (SI "v2si")
(V2SF "v2sf") (V4SF "v2sf")
(V2DF "df")])
+;; Number of units in VCOND.
+(define_mode_attr vcond_nunits [(HI "4") (SI "2")
+ (V2HI "4")
+ (V4HI "4") (V8HI "4")
+ (V2SI "2") (V4SI "2")
+ (QI "8") (V2QI "8")
+ (V4QI "8")
+ (DI "1") (V2DI "1")
+ (HF "4") (V2HF "4")
+ (V4HF "4") (V8HF "4")
+ (BF "4") (V2BF "4")
+ (SF "2")
+ (V2SF "2") (V4SF "2")
+ (V2DF "1")])
+
;; 128-bit container modes the inner or scalar source mode.
(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
(V4QI "V16QI") (V2QI "V16QI")
@@ -2107,6 +2122,22 @@ (define_mode_attr vconq [(V8QI "v16qi") (V16QI "v16qi")
(HI "v8hi") (QI "v16qi")
(SF "v4sf") (DF "v2df")])
+;; Number of units in VCONQ.
+(define_mode_attr vconq_nunits [(V8QI "16") (V16QI "16")
+ (V4QI "16") (V2QI "16")
+ (V4HI "8") (V8HI "8")
+ (V2HI "8")
+ (V2SI "4") (V4SI "4")
+ (DI "2") (V2DI "2")
+ (V4HF "8") (V8HF "8")
+ (V2HF "8") (HF "8")
+ (V4BF "8") (V8BF "8")
+ (V2BF "8") (BF "8")
+ (V2SF "4") (V4SF "4")
+ (V2DF "2") (SI "4")
+ (HI "8") (QI "16")
+ (SF "4") (DF "2")])
+
;; SVE container modes for duplication into a full SVE register.
(define_mode_attr VCONSV [(V8QI "VNx16QI") (V4QI "VNx16QI")
(V2QI "VNx16QI") (QI "VNx16QI")
@@ -2688,6 +2719,16 @@ (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
(V4HF "V8HF") (V8HF "V4HF")
(DF "V2DF") (V2DF "DF")])
+;; Number of units in VSWAP_WIDTH.
+(define_mode_attr vswap_width_nunits [(V8QI "16") (V16QI "8")
+ (V4HI "8") (V8HI "4")
+ (V8BF "4") (V4BF "8")
+ (V2SI "4") (V4SI "2")
+ (DI "2") (V2DI "1")
+ (V2SF "4") (V4SF "2")
+ (V4HF "8") (V8HF "4")
+ (DF "2") (V2DF "1")])
+
(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
(V4HI "to_128") (V8HI "to_64")
(V2SI "to_128") (V4SI "to_64")
