On Mon, Sep 28, 2026 at 10:38 AM Dominic P <[email protected]> wrote: > > Hi Tamar, > > With this patch, -O3 -mcpu=neoverse-n1 (likewise cortex-a76 and cortex-a72) > picks a one-row V2SI loop for the half-pel SAD, costed 16, over the two-row > V16QI loop, costed 59. Of the 59, 27 is three vec_construct at 9 that are > one zip1 each, and the 128-bit SAD_EXPR costs 6 against 2 for the 64-bit > one although with +dotprod both are uabd+udot. No term charges the one-row > loop for its extra loop control. On a Cortex-A72 (Pi 400, PMU cycles) the > V2SI loop is 8.5% slower for 64-row blocks. Separately, on that A72 the > x264 SAD kernels built with -mcpu=cortex-a72 take 5 to 14% more cycles > than with generic tuning. > Which would you prefer: cost fixes for these tunings, or issue info for > them?
ENOPATCH > > Thanks, > Dominic
