On 9/29/26 12:54, Richard Earnshaw (foss) wrote:
On 29/09/2026 09:21, Christophe Lyon wrote:
These tests have useless dg-skip-if directives which can be replaced
with the appropriate dg-require-effective-target and dg-add-options
directives.
This makes these tests go from UNSUPPORTED to PASS when running the
testsuite with -march options.
For gcc.target/arm/armv6-unaligned-load-ice.c, dg-add-options
arm_arch_v6k did not match dg-require-effective-target
arm_arch_v6k_thumb_ok. Fix it, and remove -mthumb and
-mfloat-abi=softfp from dg-options.
gcc/testsuite/ChangeLog:
* gcc.target/arm/armv6-unaligned-load-ice.c: Remove dg-skip-if,
fix dg-options and dg-add-options.
* gcc.target/arm/attr-unaligned-load-ice.c: Remove dg-skip-if and
fix dg-options.
* gcc.target/arm/attr_arm-err.c: Remove dg-skip-if.
* gcc.target/arm/combine-cmp-shift.c: Remove dg-skip-if and
require arm_arch_v7a.
* gcc.target/arm/lob2.c: Remove dg-skip-if, and require
arm_arch_v8_1m_main.
* gcc.target/arm/lob5.c: Likewise.
* gcc.target/arm/pr50305.c: Remove dg-skip-if and require
arm_arch_v7a_arm.
---
gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c | 6 ++----
gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c | 3 +--
gcc/testsuite/gcc.target/arm/attr_arm-err.c | 1 -
gcc/testsuite/gcc.target/arm/combine-cmp-shift.c | 3 ++-
gcc/testsuite/gcc.target/arm/lob2.c | 5 +++--
gcc/testsuite/gcc.target/arm/lob5.c | 5 +++--
gcc/testsuite/gcc.target/arm/pr50305.c | 5 +++--
7 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c
b/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c
index 886a0129f85..d61bb9ec386 100644
--- a/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c
+++ b/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c
@@ -1,9 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } {
"-march=armv6k" } } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } {
"" } } */
/* { dg-require-effective-target arm_arch_v6k_thumb_ok } */
-/* { dg-options "-mthumb -Os -mfloat-abi=softfp" } */
-/* { dg-add-options arm_arch_v6k } */
+/* { dg-options "-Os" } */
+/* { dg-add-options arm_arch_v6k_thumb } */
long
get_number (char *s, long size, int unsigned_p)
diff --git a/gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c
b/gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c
index 2eeb5220545..bae261a5e1d 100644
--- a/gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c
+++ b/gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c
@@ -1,9 +1,8 @@
/* PR target/68617
Verify that unaligned_access is correctly with attribute target. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } {
"-march=armv6" } } */
/* { dg-require-effective-target arm_arch_v6_ok } */
-/* { dg-options "-Os -mfloat-abi=softfp -mtp=soft" } */
+/* { dg-options "-Os -mtp=soft" } */
/* { dg-add-options arm_arch_v6 } */
long __attribute__((target("thumb")))
diff --git a/gcc/testsuite/gcc.target/arm/attr_arm-err.c
b/gcc/testsuite/gcc.target/arm/attr_arm-err.c
index 67d572ab2f3..d6724e46904 100644
--- a/gcc/testsuite/gcc.target/arm/attr_arm-err.c
+++ b/gcc/testsuite/gcc.target/arm/attr_arm-err.c
@@ -1,6 +1,5 @@
/* Check that attribute target arm is rejected for M profile. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } {
"-march=armv6-m" } } */
/* { dg-require-effective-target arm_arch_v6m_ok } */
/* { dg-add-options arm_arch_v6m } */
diff --git a/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c b/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
index 21d147840b8..dbcdeb9a162 100644
--- a/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
+++ b/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
@@ -1,6 +1,7 @@
-/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } {
"-march=armv7-a" } } */
/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } {
"-mpure-code" } } */
+/* { dg-require-effective-target arm_arch_v7a_ok } */
/* { dg-options "-O2 -mcpu=cortex-a8" } */
The -mcpu here will get unset by the subsequent arm_arch_v7a, I think. So it
might as well be removed. Or maybe the test should be changed to use
arm_cpu_cortex_a8, adding that to the CPU table if it's not already there.
Indeed, it turns out it's not needed.
+/* { dg-add-options arm_arch_v7a } */
/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */
typedef int SItype __attribute__ ((mode (SI)));
diff --git a/gcc/testsuite/gcc.target/arm/lob2.c
b/gcc/testsuite/gcc.target/arm/lob2.c
index d174857b926..1e13938e9f1 100644
--- a/gcc/testsuite/gcc.target/arm/lob2.c
+++ b/gcc/testsuite/gcc.target/arm/lob2.c
@@ -1,8 +1,9 @@
/* Check that GCC does not generate Armv8.1-M low over head loop instructions
if a non-inlineable function call takes place inside the loop. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp -mthumb -O3 --save-temps" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-options "-O3 --save-temps" } */
+/* { dg-add-options arm_arch_v8_1m_main } */
#include <stdlib.h>
#include "lob.h"
diff --git a/gcc/testsuite/gcc.target/arm/lob5.c b/gcc/testsuite/gcc.target/arm/lob5.c
index df5383b4a26..eb2e36213ba 100644
--- a/gcc/testsuite/gcc.target/arm/lob5.c
+++ b/gcc/testsuite/gcc.target/arm/lob5.c
@@ -2,8 +2,9 @@
instructions. Innermost loop has no fixed number of iterations
therefore is not optimizable. Outer loops are not optimized. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp -mthumb -O3 --save-temps" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-options "-O3 --save-temps" } */
+/* { dg-add-options arm_arch_v8_1m_main } */
#include <stdlib.h>
#include "lob.h"
diff --git a/gcc/testsuite/gcc.target/arm/pr50305.c b/gcc/testsuite/gcc.target/arm/pr50305.c
index f93df9f4e7e..499504121ef 100644
--- a/gcc/testsuite/gcc.target/arm/pr50305.c
+++ b/gcc/testsuite/gcc.target/arm/pr50305.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
-/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } {
"-march=armv7-a" } } */
/* { dg-skip-if "-mpure-code supports M-profile only" { *-*-* } {
"-mpure-code" } } */
-/* { dg-options "-O2 -fno-omit-frame-pointer -marm -march=armv7-a -mfpu=vfp3"
} */
+/* { dg-require-effective-target arm_arch_v7a_arm_ok } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -mfpu=vfp3" } */
+/* { dg-add-options arm_arch_v7a_arm } */
struct event {
unsigned long long id;
OK once combine-cmp-shift.c is resolved; see comment above.
Pushing with -mcpu=cortex-a8 removed in combine-cmp-shift.c.
OK to backport to gcc-14, gcc-15 and gcc-16? (applies cleanly)
Thanks,
Christophe
R.
