Ping. Please review.
On Wed, 2026-09-09 at 15:48 +0530, Avinash Jayakar wrote: > Hi, > > Updated this patch, as we split the documentation for relevant > builtins > in their own patches. > Please use this patch to review with the latest v2 version sent for > the > first patch in sequence. > https://gcc.gnu.org/pipermail/gcc-patches/2026-September/730548.html > > Changes from v1: > - Add only sha3 related documentation in extend.texi > > Thanks, > Avinash > > This patch adds new builtins for SHA3 instructions which may or may > not > be supported in a future processor. The names of the builtins may > change. Also all sha related builtins are documented. > > Core sha3 builtin: > void __builtin_dmsha3hash (__dmr2048*, uint5); > > Extended mnemonics: > void __builtin_dmsha3dw (__dmr2048*); > void __builtin_dmcryshash (__dmr2048*); > > 2026-09-09 Avinash Jayakar <[email protected]> > > gcc/ChangeLog: > * config/rs6000/crypto.md (UNSPEC_DMSHA3HASH): New unspec > entry. > (UNSPEC_DMSHA3DW): Likewise. > (UNSPEC_DMCRYSHASH): Likewise. > (SHA3_code): Iterator for sha3 extended mnemonics. > (SHA3_insn): Attribute for sha3 extended mnemonics. > (<SHA3_insn>): New define_insn for sha3 extended mnemonics. > * config/rs6000/rs6000-builtins.def: Add new builtin > definitions. > * doc/extend.texi: Document sha3 related builtins. > > gcc/testsuite/ChangeLog: > * gcc.target/powerpc/sha-builtins-5.c: New test. > --- > gcc/config/rs6000/crypto.md | 25 +++++++++++++++++ > gcc/config/rs6000/rs6000-builtins.def | 18 ++++++++++++ > gcc/doc/extend.texi | 8 +++++- > .../gcc.target/powerpc/sha-builtins-5.c | 28 > +++++++++++++++++++ > 4 files changed, 78 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/powerpc/sha-builtins-5.c > > diff --git a/gcc/config/rs6000/crypto.md > b/gcc/config/rs6000/crypto.md > index 06f9d000197..394f5d44cdd 100644 > --- a/gcc/config/rs6000/crypto.md > +++ b/gcc/config/rs6000/crypto.md > @@ -60,6 +60,9 @@ (define_c_enum "unspec" > UNSPEC_DMXXSHAKE128PAD > UNSPEC_DMXXSHA384512PAD > UNSPEC_DMXXSHA224256PAD > + UNSPEC_DMSHA3HASH > + UNSPEC_DMSHA3DW > + UNSPEC_DMCRYSHASH > UNSPEC_XXGFMUL128 > UNSPEC_XXGFMUL128GCM > UNSPEC_XXGFMUL128XTS]) > @@ -101,6 +104,13 @@ (define_int_iterator SHA2_code > [UNSPEC_DMSHA256HASH > (define_int_attr SHA2_insn [(UNSPEC_DMSHA256HASH "dmsha256hash") > (UNSPEC_DMSHA512HASH "dmsha512hash")]) > > +;; Iterator and attribute for SHA3 extended mnemonics > +(define_int_iterator SHA3_code [UNSPEC_DMSHA3DW > + UNSPEC_DMCRYSHASH]) > +(define_int_attr SHA3_insn [(UNSPEC_DMSHA3DW "dmsha3dw") > + (UNSPEC_DMCRYSHASH "dmcryshash")]) > + > + > ;; Iterator and attribute for SHAPAD extended mnemonics > (define_int_iterator SHAPAD_code [UNSPEC_DMXXSHA3512PAD > UNSPEC_DMXXSHA3384PAD > @@ -293,3 +303,18 @@ (define_insn "<SHA2PAD_insn>" > SHA2PAD_code))] > "TARGET_FUTURE" > "<SHA2PAD_insn> %0,%2") > + > +(define_insn "dmsha3hash" > + [(set (match_operand:QDO 0 "dmr_register_operand" "=wD") > + (unspec:QDO [(match_operand:QDO 1 "dmr_register_operand" "0") > + (match_operand:SI 2 "u5bit_cint_operand" "n")] > + UNSPEC_DMSHA3HASH))] > + "TARGET_FUTURE" > + "dmsha3hash %0,%2") > + > +(define_insn "<SHA3_insn>" > + [(set (match_operand:QDO 0 "dmr_register_operand" "=wD") > + (unspec:QDO [(match_operand:QDO 1 "dmr_register_operand" "0")] > + SHA3_code))] > + "TARGET_FUTURE" > + "<SHA3_insn> %0") > diff --git a/gcc/config/rs6000/rs6000-builtins.def > b/gcc/config/rs6000/rs6000-builtins.def > index 1be92fda977..ca3bdd8a579 100644 > --- a/gcc/config/rs6000/rs6000-builtins.def > +++ b/gcc/config/rs6000/rs6000-builtins.def > @@ -4385,3 +4385,21 @@ > > dmr1024 __builtin_dmxxsha224256pad_internal (dmr1024, vuc); > DMXXSHA224256PAD_INTERNAL dmxxsha224256pad {dm} > + > + void __builtin_dmsha3hash (dmr2048 *, const int<5>); > + DMSHA3HASH nothing {dm,dmint,dmr} > + > + dmr2048 __builtin_dmsha3hash_internal (dmr2048, const int<5>); > + DMSHA3HASH_INTERNAL dmsha3hash {dm} > + > + void __builtin_dmsha3dw (dmr2048 *); > + DMSHA3DW nothing {dm,dmint,dmr} > + > + dmr2048 __builtin_dmsha3dw_internal (dmr2048); > + DMSHA3DW_INTERNAL dmsha3dw {dm} > + > + void __builtin_dmcryshash (dmr2048 *); > + DMCRYSHASH nothing {dm,dmint,dmr} > + > + dmr2048 __builtin_dmcryshash_internal (dmr2048); > + DMCRYSHASH_INTERNAL dmcryshash {dm} > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 757e3ff742b..d182af355cd 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -27193,7 +27193,7 @@ vec_t __builtin_galois_field_mult_xts (vec_t, > vec_t); > > Future ISA of the PowerPC may add new instructions for accelerating > SHA > hash function. GCC provides support for these new instructions > through the > -following built-in functions. > +following built-in functions. The __dmr2048 type is a 2048 bit > integer type. > > @smallexample > void __builtin_dmsha2hash (__dmr1024*, __dmr1024*, uint1); > @@ -27219,6 +27219,12 @@ void __builtin_dmxxshake128pad (__dmr1024*, > vec_t, uint1); > void __builtin_dmxxsha384512pad (__dmr1024*, vec_t); > > void __builtin_dmxxsha224256pad (__dmr1024*, vec_t); > + > +void __builtin_dmsha3hash (__dmr2048*, uint5); > + > +void __builtin_dmsha3dw (__dmr2048*); > + > +void __builtin_dmcryshash (__dmr2048*); > @end smallexample > > @subsubheading PowerPC Vector Integer Multiply High Built-in > Functions > diff --git a/gcc/testsuite/gcc.target/powerpc/sha-builtins-5.c > b/gcc/testsuite/gcc.target/powerpc/sha-builtins-5.c > new file mode 100644 > index 00000000000..bdb9411dfef > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/sha-builtins-5.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_future_compile_ok } */ > +/* { dg-require-effective-target lp64 } */ > +/* { dg-options "-mdejagnu-cpu=future -O2" } */ > + > +void sha3hash (__dmr2048* dst) > +{ > + __builtin_dmsha3hash (dst, 31); > +} > + > +void sha3dw (__dmr2048* dst) > +{ > + __builtin_dmsha3dw (dst); > +} > + > +void cryshash (__dmr2048* dst) > +{ > + __builtin_dmcryshash (dst); > +} > + > +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ > +/* { dg-final { scan-assembler-times {\mstxvp\M} 24 } } */ > +/* { dg-final { scan-assembler-times {\mdmxxinstdmr512\M} 12 } } */ > +/* { dg-final { scan-assembler-times {\mdmxxextfdmr512\M} 12 } } */ > + > +/* { dg-final { scan-assembler-times {\mdmsha3hash\M} 1 } } */ > +/* { dg-final { scan-assembler-times {\mdmsha3dw\M} 1 } } */ > +/* { dg-final { scan-assembler-times {\mdmcryshash\M} 1 } } */
