This series replaces the existing support for reductions in SIMT with a new approach that pushes the choice of algorithm into the back-end.
Patch 1 makes the changes in the middle-end and NVPTX. Patch 2 adds new support to the AMD GCN back-end. This portion depends on the SIMT patch series already posted. I've tested this lightly, using BabelStream, and will do a full retest before the final commit. The NVPTX results are the same (or possibly slightly faster), and the AMD results are in line with expectations (there's no previous implementation to compare with). OK for mainline? (Once the dependencies are committed.) Andrew Stubbs (2): nvptx, openmp: Move SIMT reductions to the backend amdgcn: Implement SIMT reductions gcc/config/gcn/gcn-simt-vectorize.cc | 24 +++++++++++++- gcc/config/gcn/gcn-valu.md | 41 +++++++++++++++++++----- gcc/config/gcn/gcn.md | 31 ++++++++++-------- gcc/config/nvptx/nvptx-protos.h | 1 + gcc/config/nvptx/nvptx.cc | 21 ++++++++++++ gcc/config/nvptx/nvptx.md | 12 +++---- gcc/doc/ifn.texi | 8 ++--- gcc/internal-fn.cc | 31 +++++++++++++----- gcc/internal-fn.def | 2 +- gcc/omp-low.cc | 48 ++++------------------------ gcc/omp-offload.cc | 2 +- gcc/target-insns.def | 2 +- gcc/tree-cfg.cc | 7 ++-- 13 files changed, 143 insertions(+), 87 deletions(-) -- 2.54.0
