A couple more things found with LLM review. You'll notice these are
outside bitmanip as the LLM review is working well enough to start
examination of the other md files for the RISC-V port. Plan is to cover
the whole port before widening to new targets.
These are both instances where we use [U]INTVAL on an immediate_operand
without being 100% sure the object is a CONST_INT.
Tested on riscv32-elf and riscv64-elf. k3 and c920 are in flight, k1
queued.
Given the clean test on the ELF platforms and trivialness of the fix,
I'm pushing this now.
jeff
commit 8d3bac71a9433f90161a22dd13812457d32c2352
Author: Jeff Law <[email protected]>
Date: Fri Oct 23 11:04:38 2026 -0600
[RISC-V] Fix a couple more issues with unsafe [U]INTVAL checks in RISC-V
backend
A couple more things found with LLM review. You'll notice these are outside
bitmanip as the LLM review is working well enough to start examination of
the
other md files for the RISC-V port. Plan is to cover the whole port before
widening to new targets.
These are both instances where we use [U]INTVAL on an immediate_operand
without
being 100% sure the object is a CONST_INT.
Tested on riscv32-elf and riscv64-elf. k3 and c920 are in flight, k1
queued.
Given the clean test on the ELF platforms and trivialness of the fix, I'm
pushing this now.
gcc/
* config/riscv/crypto.md (riscv_xpack_<code>_<X:mode>_<HX:mode>_2):
Restrict operand 2 to const_int_operand.
* config/riscv/zicond.md (and of sign extract splitter): Similarly.
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index c3930ce4a2f..8ad673579bb 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -110,7 +110,7 @@
(define_insn "riscv_xpack_<code>_<X:mode>_<HX:mode>_2"
[(set (match_operand:X 0 "register_operand" "=r")
(oxp:X (ashift:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "immediate_operand" "n"))
+ (match_operand 2 "const_int_operand" "n"))
(zero_extend:X
(match_operand:HX 3 "register_operand" "r"))))]
"TARGET_ZBKB && INTVAL (operands[2]) == BITS_PER_WORD / 2"
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 272bee519c7..a6275f6637f 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -82,7 +82,7 @@
[(set (match_operand:X 0 "register_operand")
(and:X (sign_extract:X (match_operand:X 1 "register_operand")
(const_int 1)
- (match_operand 2 "immediate_operand"))
+ (match_operand 2 "const_int_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
"TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
