[committed][RISC-V] Remove unused and buggy pattern for testing >= 1

[Jeff Law]

LLM flagged this pattern as having a mismatch between the input RTL 
semantics and the generated assembly code semantics.

Basically we're emitting slti[u] with the last argument being a register 
when (due to using the "i" variant) the last argument must be a constant.

I'm just going to zap this pattern.  It's been in the port effectively 
forever, but it's been broken in fun and interesting ways effectively 
forever.  The breakage is such that had the pattern ever matched and 
survived to assembly output the assembler would complain loudly (which I 
have verified with the help of an RTL based test).

Assisted-By: Claude for review of the .md file and generation of the RTL 
test to trigger

Regression tested on riscv64-elf and riscv32-elf.  Pushing to the trunk.

jeffcommit 0ac3a264c9675d8aac3907bd6f33a1d38c8d72b1
Author: Jeff Law <jeffreya...@gmail.com>
Date:   Sun Oct 25 21:59:07 2026 -0600

    [RISC-V] Remove unused and buggy pattern for testing >= 1
    
    LLM flagged this pattern as having a mismatch between the input RTL 
semantics
    and the generated assembly code semantics.
    
    Basically we're emitting slti[u] with the last argument being a register 
when
    (due to using the "i" variant) the last argument must be a constant.
    
    I'm just going to zap this pattern.  It's been in the port effectively 
forever,
    but it's been broken in fun and interesting ways effectively forever.  The
    breakage is such that had the pattern ever matched and survived to assembly
    output the assembler would complain loudly (which I have verified with the 
help
    of an RTL based test).
    
    Assisted-By: Claude for review of the .md file and generation of the RTL 
test
    to trigger
    
    gcc/
            * config/riscv/riscv.md (scc >= 1 pattern): Remove dead/buggy 
pattern.

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index da6394d1ae6..3ab1cba58c4 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3896,15 +3896,6 @@
   [(set_attr "type" "slt")
    (set_attr "mode" "<X:MODE>")])
 
-(define_insn "*sge<u>_<X:mode><GPR:mode>"
-  [(set (match_operand:GPR           0 "register_operand" "=r")
-       (any_ge:GPR (match_operand:X 1 "register_operand" " r")
-                   (const_int 1)))]
-  ""
-  "slti<u>\t%0,zero,%1"
-  [(set_attr "type" "slt")
-   (set_attr "mode" "<X:MODE>")])
-
 (define_insn "@slt<u>_<X:mode><GPR:mode>3"
   [(set (match_operand:GPR           0 "register_operand" "= r")
        (any_lt:GPR (match_operand:X 1 "register_operand" "  r")