On Wed, Nov 11, 2026 at 2:36 PM Suganya Thirumurthy
<[email protected]> wrote:
>
> From: Suganya Thirumurthy <[email protected]>
>
> This patch updates the AOCL vector library support for -mveclibabi=aocl
> covering AOCL-LibM 5.3.1 and AOCL 6.0.0.
>
> gcc/ChangeLog:
>
> * config/i386/i386.cc (ix86_veclibabi_aocl): Update vector
> widths and new functions
These descriptions are too vague. Better write:
Update vector widths for tan, ...., and atanh functions. Add erfc,
cbrt and atan2 functions.
Please add full stops at the end of sentences.
> * doc/invoke.texi: Update the whole supported set
[mveclibabi]: Add amd_..., amd_... and amd_... .
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/vectorize-aocl1.c: Update test.
Also test ...
Uros.
>
> ---
> Hi,
> Bootstrapped and tested on x86_64-linux.
>
> Ok for trunk?
> Regards,
> Suganya
>
> gcc/config/i386/i386.cc | 20 ++--
> gcc/doc/invoke.texi | 63 ++++++-----
> .../gcc.target/i386/vectorize-aocl1.c | 104 +++++++++++++-----
> 3 files changed, 125 insertions(+), 62 deletions(-)
>
> diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
> index ad34cfeda02..fbdfb116948 100644
> --- a/gcc/config/i386/i386.cc
> +++ b/gcc/config/i386/i386.cc
> @@ -20725,7 +20725,7 @@ ix86_veclibabi_aocl (combined_fn fn, tree type_out,
> tree type_in)
> are used to fill out unused positions in the arrays. */
> static const int supported_n[][2][3] = {
> /* Single prec. , Double prec. */
> - { { 16, 0, 0 }, { 2, 4, 8 } }, /* TAN. */
> + { { 4, 8, 16 }, { 2, 4, 8 } }, /* TAN. */
> { { 4, 8, 16 }, { 2, 4, 8 } }, /* EXP. */
> { { 4, 8, 16 }, { 2, 4, 8 } }, /* EXP2. */
> { { 4, 8, 16 }, { 2, 4, 8 } }, /* LOG. */
> @@ -20734,15 +20734,18 @@ ix86_veclibabi_aocl (combined_fn fn, tree type_out,
> tree type_in)
> { { 4, 8, 16 }, { 2, 4, 8 } }, /* SIN. */
> { { 4, 8, 16 }, { 2, 4, 8 } }, /* POW. */
> { { 4, 8, 16 }, { 2, 4, 8 } }, /* ERF. */
> - { { 4, 8, 16 }, { 2, 8, 0 } }, /* ATAN. */
> + { { 4, 8, 16 }, { 2, 4, 8 } }, /* ATAN. */
> { { 4, 8, 16 }, { 2, 0, 0 } }, /* LOG10. */
> - { { 4, 0, 0 }, { 2, 0, 0 } }, /* EXP10. */
> + { { 4, 8, 16 }, { 2, 4, 8 } }, /* EXP10. */
> { { 4, 0, 0 }, { 2, 0, 0 } }, /* LOG1P. */
> - { { 4, 8, 16 }, { 8, 0, 0 } }, /* ASIN. */
> - { { 4, 16, 0 }, { 0, 0, 0 } }, /* ACOS. */
> - { { 4, 8, 16 }, { 0, 0, 0 } }, /* TANH. */
> + { { 4, 8, 16 }, { 2, 4, 8 } }, /* ASIN. */
> + { { 4, 8, 16 }, { 2, 4, 8 } }, /* ACOS. */
> + { { 4, 8, 16 }, { 2, 4, 8 } }, /* TANH. */
> { { 4, 0, 0 }, { 0, 0, 0 } }, /* EXPM1. */
> - { { 4, 8, 0 }, { 0, 0, 0 } }, /* COSH. */
> + { { 4, 8, 16 }, { 2, 4, 8 } }, /* COSH. */
> + { { 4, 8, 16 }, { 2, 4, 8 } }, /* ERFC. */
> + { { 4, 8, 0 }, { 2, 0, 0 } }, /* CBRT. */
> + { { 0, 0, 0 }, { 2, 4, 8 } }, /* ATAN2. */
> };
>
> /* We cannot simply index the supported_n array with FN since multiple FNs
> @@ -20769,6 +20772,9 @@ ix86_veclibabi_aocl (combined_fn fn, tree type_out,
> tree type_in)
> CASE_CFN_TANH : i = 15; break;
> CASE_CFN_EXPM1 : i = 16; break;
> CASE_CFN_COSH : i = 17; break;
> + CASE_CFN_ERFC : i = 18; break;
> + CASE_CFN_CBRT : i = 19; break;
> + CASE_CFN_ATAN2 : i = 20; break;
> default: return NULL_TREE;
> }
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index ef9cb025c22..b17b996677b 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -37039,32 +37039,43 @@ GCC currently emits calls to @code{vmldExp2},
> @code{vmldLn2},
> @code{vmlsSinh4}, @code{vmlsSin4}, @code{vmlsAsinh4}, @code{vmlsAsin4},
> @code{vmlsCosh4}, @code{vmlsCos4}, @code{vmlsAcosh4} and @code{vmlsAcos4} for
> corresponding function type when @option{-mveclibabi=svml} is used,
> -@code{amd_vrs4_acosf}, @code{amd_vrs16_acosf}, @code{amd_vrd8_asin},
> -@code{amd_vrs4_asinf}, @code{amd_vrs8_asinf}, @code{amd_vrs16_asinf},
> -@code{amd_vrd2_atan}, @code{amd_vrd8_atan}, @code{amd_vrs4_atanf},
> -@code{amd_vrs8_atanf}, @code{amd_vrs16_atanf}, @code{amd_vrd2_cos},
> -@code{amd_vrd4_cos}, @code{amd_vrd8_cos}, @code{amd_vrs4_cosf},
> -@code{amd_vrs8_cosf}, @code{amd_vrs16_cosf}, @code{amd_vrs4_coshf},
> -@code{amd_vrs8_coshf}, @code{amd_vrd2_erf}, @code{amd_vrd4_erf},
> -@code{amd_vrd8_erf}, @code{amd_vrs4_erff}, @code{amd_vrs8_erff},
> -@code{amd_vrs16_erff}, @code{amd_vrd2_exp}, @code{amd_vrd4_exp},
> -@code{amd_vrd8_exp}, @code{amd_vrs4_expf}, @code{amd_vrs8_expf},
> -@code{amd_vrs16_expf}, @code{amd_vrd2_exp10}, @code{amd_vrs4_exp10f},
> -@code{amd_vrd2_exp2}, @code{amd_vrd4_exp2}, @code{amd_vrd8_exp2},
> -@code{amd_vrs4_exp2f}, @code{amd_vrs8_exp2f}, @code{amd_vrs16_exp2f},
> -@code{amd_vrs4_expm1f}, @code{amd_vrd2_log}, @code{amd_vrd4_log},
> -@code{amd_vrd8_log}, @code{amd_vrs4_logf}, @code{amd_vrs8_logf},
> -@code{amd_vrs16_logf}, @code{amd_vrd2_log10}, @code{amd_vrs4_log10f},
> -@code{amd_vrs8_log10f}, @code{amd_vrs16_log10f}, @code{amd_vrd2_log1p},
> -@code{amd_vrs4_log1pf}, @code{amd_vrd2_log2}, @code{amd_vrd4_log2},
> -@code{amd_vrd8_log2}, @code{amd_vrs4_log2f}, @code{amd_vrs8_log2f},
> -@code{amd_vrs16_log2f}, @code{amd_vrd2_pow}, @code{amd_vrd4_pow},
> -@code{amd_vrd8_pow}, @code{amd_vrs4_powf}, @code{amd_vrs8_powf},
> -@code{amd_vrs16_powf}, @code{amd_vrd2_sin}, @code{amd_vrd4_sin},
> -@code{amd_vrd8_sin}, @code{amd_vrs4_sinf}, @code{amd_vrs8_sinf},
> -@code{amd_vrs16_sinf}, @code{amd_vrd2_tan}, @code{amd_vrd4_tan},
> -@code{amd_vrd8_tan}, @code{amd_vrs16_tanf}, @code{amd_vrs4_tanhf},
> -@code{amd_vrs8_tanhf}, @code{amd_vrs16_tanhf} for the corresponding function
> +@code{amd_vrd2_acos}, @code{amd_vrd2_asin}, @code{amd_vrd2_atan},
> +@code{amd_vrd2_atan2}, @code{amd_vrd2_cbrt}, @code{amd_vrd2_cos},
> +@code{amd_vrd2_cosh}, @code{amd_vrd2_erf}, @code{amd_vrd2_erfc},
> +@code{amd_vrd2_exp}, @code{amd_vrd2_exp10}, @code{amd_vrd2_exp2},
> +@code{amd_vrd2_log}, @code{amd_vrd2_log10}, @code{amd_vrd2_log1p},
> +@code{amd_vrd2_log2}, @code{amd_vrd2_pow}, @code{amd_vrd2_sin},
> +@code{amd_vrd2_tan}, @code{amd_vrd2_tanh}, @code{amd_vrd4_acos},
> +@code{amd_vrd4_asin}, @code{amd_vrd4_atan}, @code{amd_vrd4_atan2},
> +@code{amd_vrd4_cos}, @code{amd_vrd4_cosh}, @code{amd_vrd4_erf},
> +@code{amd_vrd4_erfc}, @code{amd_vrd4_exp}, @code{amd_vrd4_exp10},
> +@code{amd_vrd4_exp2}, @code{amd_vrd4_log}, @code{amd_vrd4_log2},
> +@code{amd_vrd4_pow}, @code{amd_vrd4_sin}, @code{amd_vrd4_tan},
> +@code{amd_vrd4_tanh}, @code{amd_vrd8_acos}, @code{amd_vrd8_asin},
> +@code{amd_vrd8_atan}, @code{amd_vrd8_atan2}, @code{amd_vrd8_cos},
> +@code{amd_vrd8_cosh}, @code{amd_vrd8_erf}, @code{amd_vrd8_erfc},
> +@code{amd_vrd8_exp}, @code{amd_vrd8_exp10}, @code{amd_vrd8_exp2},
> +@code{amd_vrd8_log}, @code{amd_vrd8_log2}, @code{amd_vrd8_pow},
> +@code{amd_vrd8_sin}, @code{amd_vrd8_tan}, @code{amd_vrd8_tanh},
> +@code{amd_vrs16_acosf}, @code{amd_vrs16_asinf}, @code{amd_vrs16_atanf},
> +@code{amd_vrs16_cosf}, @code{amd_vrs16_coshf}, @code{amd_vrs16_erfcf},
> +@code{amd_vrs16_erff}, @code{amd_vrs16_exp10f}, @code{amd_vrs16_exp2f},
> +@code{amd_vrs16_expf}, @code{amd_vrs16_log10f}, @code{amd_vrs16_log2f},
> +@code{amd_vrs16_logf}, @code{amd_vrs16_powf}, @code{amd_vrs16_sinf},
> +@code{amd_vrs16_tanf}, @code{amd_vrs16_tanhf}, @code{amd_vrs4_acosf},
> +@code{amd_vrs4_asinf}, @code{amd_vrs4_atanf}, @code{amd_vrs4_cbrtf},
> +@code{amd_vrs4_cosf}, @code{amd_vrs4_coshf}, @code{amd_vrs4_erfcf},
> +@code{amd_vrs4_erff}, @code{amd_vrs4_exp10f}, @code{amd_vrs4_exp2f},
> +@code{amd_vrs4_expf}, @code{amd_vrs4_expm1f}, @code{amd_vrs4_log10f},
> +@code{amd_vrs4_log1pf}, @code{amd_vrs4_log2f}, @code{amd_vrs4_logf},
> +@code{amd_vrs4_powf}, @code{amd_vrs4_sinf}, @code{amd_vrs4_tanf},
> +@code{amd_vrs4_tanhf}, @code{amd_vrs8_acosf}, @code{amd_vrs8_asinf},
> +@code{amd_vrs8_atanf}, @code{amd_vrs8_cbrtf}, @code{amd_vrs8_cosf},
> +@code{amd_vrs8_coshf}, @code{amd_vrs8_erfcf}, @code{amd_vrs8_erff},
> +@code{amd_vrs8_exp10f}, @code{amd_vrs8_exp2f}, @code{amd_vrs8_expf},
> +@code{amd_vrs8_log10f}, @code{amd_vrs8_log2f}, @code{amd_vrs8_logf},
> +@code{amd_vrs8_powf}, @code{amd_vrs8_sinf}, @code{amd_vrs8_tanf},
> +and @code{amd_vrs8_tanhf} for the corresponding function
> type when @option{-mveclibabi=aocl} is used, and @code{__vrd2_sin},
> @code{__vrd2_cos}, @code{__vrd2_exp}, @code{__vrd2_log}, @code{__vrd2_log2},
> @code{__vrd2_log10}, @code{__vrs4_sinf}, @code{__vrs4_cosf},
> diff --git a/gcc/testsuite/gcc.target/i386/vectorize-aocl1.c
> b/gcc/testsuite/gcc.target/i386/vectorize-aocl1.c
> index 18c098aeed0..d23a3231c40 100644
> --- a/gcc/testsuite/gcc.target/i386/vectorize-aocl1.c
> +++ b/gcc/testsuite/gcc.target/i386/vectorize-aocl1.c
> @@ -22,6 +22,8 @@ float asinf(float);
> float acosf(float);
> float tanhf(float);
> float coshf(float);
> +float erfcf(float);
> +float cbrtf(float);
>
> double tan(double);
> double exp(double);
> @@ -41,6 +43,9 @@ double asin(double);
> double acos(double);
> double tanh(double);
> double cosh(double);
> +double erfc(double);
> +double cbrt(double);
> +double atan2(double, double);
>
> #define gentest1(FUN, BASE, VF) \
> extern BASE s_##FUN##_##BASE##_##VF[VF]; \
> @@ -66,13 +71,13 @@ double cosh(double);
> } \
>
>
> -gentest1(tan, float, 16)
> -
> #define COMMON_FLOAT_TESTS1(FUN) \
> gentest1(FUN, float, 4) \
> gentest1(FUN, float, 8) \
> gentest1(FUN, float, 16)
>
> +COMMON_FLOAT_TESTS1(tanf)
> +
> COMMON_FLOAT_TESTS1(exp)
> COMMON_FLOAT_TESTS1(exp2)
> COMMON_FLOAT_TESTS1(log)
> @@ -90,22 +95,24 @@ COMMON_FLOAT_TESTS1(erf)
> //gentest1(fabsf, float, 4) provided by an instruction
> //gentest1(fabsf, float, 8) provided by an instruction
>
> -COMMON_FLOAT_TESTS1(atan)
> -COMMON_FLOAT_TESTS1(log10)
> +COMMON_FLOAT_TESTS1(atanf)
> +COMMON_FLOAT_TESTS1(log10f)
>
> -gentest1(exp10f, float, 4)
> +COMMON_FLOAT_TESTS1(exp10f)
> gentest1(expm1f, float, 4)
> gentest1(log1pf, float, 4)
>
> COMMON_FLOAT_TESTS1(asinf)
> -
> -gentest1(acosf, float, 4)
> -gentest1(acosf, float, 16)
> +COMMON_FLOAT_TESTS1(acosf)
>
> COMMON_FLOAT_TESTS1(tanhf)
>
> -gentest1(coshf, float, 4)
> -gentest1(coshf, float, 8)
> +COMMON_FLOAT_TESTS1(coshf)
> +
> +COMMON_FLOAT_TESTS1(erfcf)
> +
> +gentest1(cbrtf, float, 4)
> +gentest1(cbrtf, float, 8)
>
> #define COMMON_DOUBLE_TESTS1(FUN) \
> gentest1(FUN, double, 2) \
> @@ -131,15 +138,25 @@ COMMON_DOUBLE_TESTS1(erf)
> //gentest1(fabs, double, 2) provided by an instruction
> //gentest1(fabs, double, 4) provided by an instruction
>
> -gentest1(atan, double, 2)
> -gentest1(atan, double, 8)
> +COMMON_DOUBLE_TESTS1(atan)
> +COMMON_DOUBLE_TESTS1(exp10)
>
> gentest1(log10, double, 2)
> -gentest1(exp10, double, 2)
> gentest1(expm1, double, 2)
> gentest1(log1p, double, 2)
>
> -gentest1(asin, double, 8)
> +COMMON_DOUBLE_TESTS1(asin)
> +COMMON_DOUBLE_TESTS1(acos)
> +COMMON_DOUBLE_TESTS1(erfc)
> +
> +gentest1(cbrt, double, 2)
> +
> +COMMON_DOUBLE_TESTS1(tanh)
> +COMMON_DOUBLE_TESTS1(cosh)
> +
> +gentest2(atan2, double, 2)
> +gentest2(atan2, double, 4)
> +gentest2(atan2, double, 8)
>
>
> /* { dg-final { scan-assembler-times "amd_vrs8_expf" 1 } } */
> @@ -180,31 +197,31 @@ gentest1(asin, double, 8)
> /* { dg-final { scan-assembler-times "amd_vrs4_sinf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs8_sinf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrd4_sin" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd4_cos" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd4_tan" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd2_cos" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd4_cos\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd4_tan\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd2_cos\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrd2_sin" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd2_tan" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd2_tan\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs16_cosf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs16_sinf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs16_tanf" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd8_cos" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd8_cos\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrd8_sin" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd8_tan" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd8_tan\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs4_acosf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs4_asinf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs8_asinf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs4_atanf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs8_atanf" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd2_atan" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd2_atan\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs16_atanf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs16_asinf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs16_acosf" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd8_atan" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd8_atan\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrd8_asin" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs4_coshf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs4_tanhf" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrs8_coshf" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrs8_coshf\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs8_tanhf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs16_tanhf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs4_powf" 1 } } */
> @@ -214,11 +231,40 @@ gentest1(asin, double, 8)
> /* { dg-final { scan-assembler-times "amd_vrs16_powf" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrd8_pow" 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs4_erff" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd2_erf" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd2_erf\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs8_erff" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd4_erf" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd4_erf\M} 1 } } */
> /* { dg-final { scan-assembler-times "amd_vrs16_erff" 1 } } */
> -/* { dg-final { scan-assembler-times "amd_vrd8_erf" 1 } } */
> -
> -
> -
> +/* { dg-final { scan-assembler-times {\mamd_vrd8_erf\M} 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs4_tanf" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs8_tanf" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs8_acosf" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd4_atan\M} 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd2_cosh" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs8_exp10f" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs16_exp10f" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd8_exp10" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd2_asin" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd4_asin" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd2_acos" 1 } } */
> +/* { dg-final { scan-assembler-times {\mamd_vrd4_acos\M} 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs4_erfcf" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs8_erfcf" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs16_erfcf" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd2_erfc" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd4_erfc" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd8_erfc" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs4_cbrtf" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs8_cbrtf" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd2_cbrt" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd4_exp10" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd8_acos" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrs16_coshf" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd4_cosh" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd8_cosh" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd2_tanh" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd4_tanh" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd8_tanh" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd2_atan2" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd4_atan2" 1 } } */
> +/* { dg-final { scan-assembler-times "amd_vrd8_atan2" 1 } } */
> --
> 2.34.1
>
