Add negative-count rotation reversal to simplify-rtx, as suggested
by Jeff. Retain the count mask to keep the reversed count in range.
Patch 1 fixes AArch64 ROR patterns that incorrectly accept masked left
rotations, a bug exposed by the generic optimization in patch 2.
Based on a89bad222e954a9c1a4f29112c75174ad4e54213.
Across the baseline and series-only builds, C/C++ selftests and
RV32/RV64 QEMU checks passed: 48 correctness runs and 16 benchmark
binaries. Performance was measured in 32 gem5 Minor/O3 runs.
Earlier x86-64 full C/C++ regression runs had unchanged results.
AArch64 targeted runtime tests passed with the prerequisite fix.
Microkernel reductions (%), for 64-bit / 32-bit rotations:
Instructions Minor cycles O3 cycles
RV64 gem5 16.66 / 14.28 0.00 / 33.21 24.97 / 24.95
x86-64 gem5 24.99 / 22.22 19.49 / 5.13 39.98 / 39.95
AArch64 gem5 0.00 / 0.00 0.00 / 0.00 0.00 / 0.00
The x86-64 and AArch64 rows use earlier target-specific gem5 runs.
AArch64 compares the prerequisite fix alone with the fix plus the generic
optimization, using two right-rotate kernels with the default SIMD settings.
RISC-V K1 broad instructions decreased 16.67% / 14.29% and cycles decreased
25.00% / 19.99%, from 15 paired measurements per kernel.
