Ports the NEON multiply-accumulate intrinsics to the pragma-based
framework, and add corresponding assembly tests for each variant.
Also deletes builtin functions that were only used by `arm_neon.h`:
* __builtin_aarch64_mla
* __builtin_aarch64_mla_n
* __builtin_aarch64_mls
* __builtin_aarch64_mls_n
* __builtin_aarch64_float_mla
* __builtin_aarch64_float_mla_n
* __builtin_aarch64_float_mls
* __builtin_aarch64_float_mls_n
* __builtin_aarch64_float_mla_lane
* __builtin_aarch64_float_mla_laneq
* __builtin_aarch64_float_mls_lane
* __builtin_aarch64_float_mls_laneq
and their corresponding expanders in `aarch64-simd.md`.
gcc/ChangeLog:
* config/aarch64/aarch64-acle-builtins.h (TYPES_neon_mla,
TYPES_neon_mla_lane): New type arrays.
* config/aarch64/aarch64-neon-builtins-base.cc (struct
multiply_accumulate): New struct.
* config/aarch64/aarch64-neon-builtins-base.def
(vmla, vmlaq, vmla_n, vmlaq_n, vmla_lane, vmla_laneq,
vmlaq_lane, vmlaq_laneq, vmls, vmlsq, vmls_n, vmlsq_n,
vmls_lane, vmls_laneq, vmlsq_lane, vmlsq_laneq): New function
declarations.
* config/aarch64/aarch64-simd-builtins.def: Delete
`__builtin_aarch64_*` functions.
* config/aarch64/aarch64-simd.md (aarch64_float_mla<mode>,
aarch64_float_mls<mode>, aarch64_float_mla_n<mode>,
aarch64_float_mls_n<mode>, aarch64_float_mla_lane<mode>,
aarch64_float_mls_lane<mode>, aarch64_float_mla_laneq<mode>,
aarch64_float_mls_laneq<mode>): Delete now-obsolete insns.
* config/aarch64/arm_neon.h: (vmla_n_f32, vmla_n_s16,
vmla_n_s32, vmla_n_u16, vmla_n_u32, vmla_s8, vmla_s16,
vmla_s32, vmla_u8, vmla_u16, vmla_u32, vmlaq_n_f32,
vmlaq_n_s16, vmlaq_n_s32, vmlaq_n_u16, vmlaq_n_u32, vmlaq_s8,
vmlaq_s16, vmlaq_s32, vmlaq_u8, vmlaq_u16, vmlaq_u32,
vmls_n_f32, vmls_n_s16, vmls_n_s32, vmls_n_u16, vmls_n_u32,
vmls_s8, vmls_s16, vmls_s32, vmls_u8, vmls_u16, vmls_u32,
vmlsq_n_f32, vmlsq_n_s16, vmlsq_n_s32, vmlsq_n_u16,
vmlsq_n_u32, vmlsq_s8, vmlsq_s16, vmlsq_s32, vmlsq_u8,
vmlsq_u16, vmlsq_u32, vmla_f32, vmla_f64, vmlaq_f32,
vmlaq_f64, vmla_lane_f32, vmla_lane_s16, vmla_lane_s32,
vmla_lane_u16, vmla_lane_u32, vmla_laneq_f32, vmla_laneq_s16,
vmla_laneq_s32, vmla_laneq_u16, vmla_laneq_u32,
vmlaq_lane_f32, vmlaq_lane_s16, vmlaq_lane_s32,
vmlaq_lane_u16, vmlaq_lane_u32, vmlaq_laneq_f32,
vmlaq_laneq_s16, vmlaq_laneq_s32, vmlaq_laneq_u16,
vmlaq_laneq_u32, vmls_f32, vmls_f64, vmlsq_f32, vmlsq_f64,
vmls_lane_f32, vmls_lane_s16, vmls_lane_s32, vmls_lane_u16,
vmls_lane_u32, vmls_laneq_f32, vmls_laneq_s16, vmls_laneq_s32,
vmls_laneq_u16, vmls_laneq_u32, vmlsq_lane_f32,
vmlsq_lane_s16, vmlsq_lane_s32, vmlsq_lane_u16,
vmlsq_lane_u32, vmlsq_laneq_f32, vmlsq_laneq_s16,
vmlsq_laneq_s32, vmlsq_laneq_u16, vmlsq_laneq_u32): Delete
function definitions.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/neon/vmla.c: New test.
* gcc.target/aarch64/neon/vmls.c: New test.
---
gcc/config/aarch64/aarch64-acle-builtins.h | 15 +
.../aarch64/aarch64-neon-builtins-base.cc | 74 ++
.../aarch64/aarch64-neon-builtins-base.def | 21 +
gcc/config/aarch64/aarch64-simd-builtins.def | 22 -
gcc/config/aarch64/aarch64-simd.md | 146 ----
gcc/config/aarch64/arm_neon.h | 694 +-----------------
gcc/testsuite/gcc.target/aarch64/neon/vmla.c | 350 +++++++++
gcc/testsuite/gcc.target/aarch64/neon/vmls.c | 350 +++++++++
8 files changed, 838 insertions(+), 834 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmla.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmls.c
diff --git a/gcc/config/aarch64/aarch64-acle-builtins.h
b/gcc/config/aarch64/aarch64-acle-builtins.h
index 3260140f1e8..3b3fdc7fe33 100644
--- a/gcc/config/aarch64/aarch64-acle-builtins.h
+++ b/gcc/config/aarch64/aarch64-acle-builtins.h
@@ -1981,6 +1981,19 @@ function_expander::result_mode () const
#define TYPES_b_neon(S, D, T) \
S (p8), S (s8), S (u8)
+/* _s8 _s16 _s32
+ _u8 _u16 _u32
+ _f32 _f64. */
+#define TYPES_neon_mla(S, D, T) \
+ TYPES_bhs_integer (S, D, T), \
+ TYPES_sd_float (S, D, T)
+
+/* _s16 _u16
+ _s32 _u32 _f32. */
+#define TYPES_neon_mla_lane(S, D, T) \
+ TYPES_hs_integer (S, D, T), \
+ TYPES_s_float (S, D, T)
+
/* _p8 _s8 _u8 _mf8. */
#define TYPES_neon_rev16(S, D, T) \
S (p8), S (s8), S (u8), S (mf8)
@@ -2232,6 +2245,8 @@ DEF_SVE_TYPES_ARRAY (bhdq_poly);
DEF_SVE_TYPES_ARRAY (bhs_neon);
DEF_SVE_TYPES_ARRAY (bhsd_neon);
DEF_SVE_TYPES_ARRAY (neon_copy_lane);
+DEF_SVE_TYPES_ARRAY (neon_mla_lane);
+DEF_SVE_TYPES_ARRAY (neon_mla);
DEF_SVE_TYPES_ARRAY (neon_rev16);
DEF_SVE_TYPES_ARRAY (neon_rev32);
DEF_SVE_TYPES_ARRAY (neon_rev64);
diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc
b/gcc/config/aarch64/aarch64-neon-builtins-base.cc
index 4dd26fd102d..bdb14273f5f 100644
--- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc
@@ -956,6 +956,69 @@ public:
}
};
+// vmla (acc, lhs, rhs) = acc + lhs * rhs
+// vmls (acc, lhs, rhs) = acc - lhs * rhs
+template <arith_kind kind, bool negate>
+struct multiply_accumulate : public gimple_function_base
+{
+ gimple *fold (gimple_folder &f) const override
+ {
+ tree acc = gimple_call_arg (f.call, 0);
+ tree lhs = gimple_call_arg (f.call, 1);
+ tree rhs = gimple_call_arg (f.call, 2);
+ tree lane_index;
+ tree ret_type = TREE_TYPE (f.lhs);
+
+ switch (kind)
+ {
+ case arith_kind::normal:
+ break;
+
+ case arith_kind::dup:
+ rhs = f.force_val (build_vec_dup (TREE_TYPE (lhs), rhs));
+ break;
+
+ case arith_kind::lane:
+ lane_index = gimple_call_arg (f.call, 3);
+ rhs = f.force_val (build_lane_get (rhs, lane_index));
+ if (VECTOR_TYPE_P (ret_type))
+ rhs = f.force_val (build_vec_dup (TREE_TYPE (lhs), rhs));
+ break;
+ }
+
+ tree_code code = negate ? MINUS_EXPR : PLUS_EXPR;
+ if (FLOAT_TYPE_P (ret_type))
+ {
+ /* Use a PAREN_EXPR (equivalent to C's `__builtin_assoc_barrier`) to
+ prevent floating-point add and mul being transformed to an FMA. */
+ auto mul = f.force_val (fold_build2 (MULT_EXPR, ret_type, lhs, rhs));
+ auto paren = f.force_val (fold_build1 (PAREN_EXPR, ret_type, mul));
+ auto addsub = f.force_val (fold_build2 (code, ret_type, acc, paren));
+ return this->maybe_optimization_barrier (f, addsub);
+ }
+ else if (!TYPE_UNSIGNED (ret_type))
+ {
+ /* Convert signed inputs to unsigned first, to avoid undefined behaviour
+ on overflow. */
+ auto signed_type = ret_type;
+ auto unsigned_type = unsigned_type_for (signed_type);
+ lhs = f.force_val (build_cast (unsigned_type, lhs));
+ rhs = f.force_val (build_cast (unsigned_type, rhs));
+ acc = f.force_val (build_cast (unsigned_type, acc));
+ auto mul = f.force_val (fold_build2 (MULT_EXPR, unsigned_type, lhs,
rhs));
+ auto addsub = f.force_val (fold_build2 (code, unsigned_type, acc, mul));
+ return gimple_build_assign (f.lhs, build_cast (signed_type, addsub));
+ }
+ else
+ {
+ auto mul = f.force_val (fold_build2 (MULT_EXPR, ret_type, lhs, rhs));
+ return gimple_build_assign (f.lhs, code, acc, mul);
+ }
+ }
+};
+template <arith_kind kind> using gimple_mla = multiply_accumulate<kind, false>;
+template <arith_kind kind> using gimple_mls = multiply_accumulate<kind, true>;
+
// Reinterpret
NEON_FUNCTION (vreinterpret, vreinterpretq, gimple_reinterpret,)
@@ -986,6 +1049,17 @@ NEON_FUNCTION (vmul_lane, vmul_laneq,
vmuls_lane, vmuls_laneq,
vmuld_lane, vmuld_laneq, gimple_arith_lane, (MULT_EXPR))
+// Multiply-accumulate
+NEON_FUNCTION (vmla, vmlaq, gimple_mla<arith_kind::normal>,)
+NEON_FUNCTION (vmla_n, vmlaq_n, gimple_mla<arith_kind::dup>,)
+NEON_FUNCTION (vmla_lane, vmla_laneq, vmlaq_lane, vmlaq_laneq,
+ gimple_mla<arith_kind::lane>,)
+
+NEON_FUNCTION (vmls, vmlsq, gimple_mls<arith_kind::normal>,)
+NEON_FUNCTION (vmls_n, vmlsq_n, gimple_mls<arith_kind::dup>,)
+NEON_FUNCTION (vmls_lane, vmls_laneq, vmlsq_lane, vmlsq_laneq,
+ gimple_mls<arith_kind::lane>,)
+
// Saturating arithmetic
NEON_FUNCTION (vqaddb, vqaddh, vqadds, vqaddd, vqadd, vqaddq, gimple_ifn,
(IFN_SAT_ADD))
NEON_FUNCTION (vqsubb, vqsubh, vqsubs, vqsubd, vqsub, vqsubq, gimple_ifn,
(IFN_SAT_SUB))
diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def
b/gcc/config/aarch64/aarch64-neon-builtins-base.def
index a42a25135a0..40aa1a656d7 100644
--- a/gcc/config/aarch64/aarch64-neon-builtins-base.def
+++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def
@@ -276,6 +276,26 @@ DEF_NEON_FUNCTION (vrndx, h_float, ("D0,D0"))
DEF_NEON_FUNCTION (vrndxq, h_float, ("Q0,Q0"))
#undef REQUIRED_EXTENSIONS
+// Multiply-accumulate
+#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD)
+DEF_NEON_FUNCTION (vmla, neon_mla, ("D0,D0,D0,D0"))
+DEF_NEON_FUNCTION (vmlaq, neon_mla, ("Q0,Q0,Q0,Q0"))
+DEF_NEON_FUNCTION (vmla_n, neon_mla_lane, ("D0,D0,D0,s0"))
+DEF_NEON_FUNCTION (vmlaq_n, neon_mla_lane, ("Q0,Q0,Q0,s0"))
+DEF_NEON_FUNCTION (vmla_lane, neon_mla_lane, ("D0,D0,D0,D0,ss32", lane<3>))
+DEF_NEON_FUNCTION (vmla_laneq, neon_mla_lane, ("D0,D0,D0,Q0,ss32", lane<3>))
+DEF_NEON_FUNCTION (vmlaq_lane, neon_mla_lane, ("Q0,Q0,Q0,D0,ss32", lane<3>))
+DEF_NEON_FUNCTION (vmlaq_laneq, neon_mla_lane, ("Q0,Q0,Q0,Q0,ss32", lane<3>))
+DEF_NEON_FUNCTION (vmls, neon_mla, ("D0,D0,D0,D0"))
+DEF_NEON_FUNCTION (vmlsq, neon_mla, ("Q0,Q0,Q0,Q0"))
+DEF_NEON_FUNCTION (vmls_n, neon_mla_lane, ("D0,D0,D0,s0"))
+DEF_NEON_FUNCTION (vmlsq_n, neon_mla_lane, ("Q0,Q0,Q0,s0"))
+DEF_NEON_FUNCTION (vmls_lane, neon_mla_lane, ("D0,D0,D0,D0,ss32", lane<3>))
+DEF_NEON_FUNCTION (vmls_laneq, neon_mla_lane, ("D0,D0,D0,Q0,ss32", lane<3>))
+DEF_NEON_FUNCTION (vmlsq_lane, neon_mla_lane, ("Q0,Q0,Q0,D0,ss32", lane<3>))
+DEF_NEON_FUNCTION (vmlsq_laneq, neon_mla_lane, ("Q0,Q0,Q0,Q0,ss32", lane<3>))
+#undef REQUIRED_EXTENSIONS
+
// Bitwise operations
#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD)
DEF_NEON_FUNCTION (vand, all_integer, ("D0,D0,D0"))
@@ -396,6 +416,7 @@ DEF_NEON_FUNCTION (vsm3partw2q, s_unsigned, ("Q0,Q0,Q0,Q0"))
DEF_NEON_FUNCTION (vsm4eq, s_unsigned, ("Q0,Q0,Q0"))
DEF_NEON_FUNCTION (vsm4ekeyq, s_unsigned, ("Q0,Q0,Q0"))
#undef REQUIRED_EXTENSIONS
+
// FP16 matrix-multiply accumulate (widening)
#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_F16F32MM)
DEF_NEON_FUNCTION (vmmlaq, cvt_f32_f16, ("Q0,Q0,Q1,Q1"))
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index 0a84dfd459d..1fb7c763990 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -233,20 +233,6 @@
BUILTIN_VQN (UNOP, xtn, 0, DEFAULT)
BUILTIN_VQN (UNOPU, xtn, 0, DEFAULT)
- /* Implemented by aarch64_mla<mode>. */
- BUILTIN_VDQ_BHSI (TERNOP, mla, 0, DEFAULT)
- BUILTIN_VDQ_BHSI (TERNOPU, mla, 0, DEFAULT)
- /* Implemented by aarch64_mla_n<mode>. */
- BUILTIN_VDQHS (TERNOP, mla_n, 0, DEFAULT)
- BUILTIN_VDQHS (TERNOPU, mla_n, 0, DEFAULT)
-
- /* Implemented by aarch64_mls<mode>. */
- BUILTIN_VDQ_BHSI (TERNOP, mls, 0, DEFAULT)
- BUILTIN_VDQ_BHSI (TERNOPU, mls, 0, DEFAULT)
- /* Implemented by aarch64_mls_n<mode>. */
- BUILTIN_VDQHS (TERNOP, mls_n, 0, DEFAULT)
- BUILTIN_VDQHS (TERNOPU, mls_n, 0, DEFAULT)
-
BUILTIN_VQN (SHIFTIMM, shrn_n, 0, DEFAULT)
BUILTIN_VQN (USHIFTIMM, shrn_n, 0, DEFAULT)
@@ -689,14 +675,6 @@
BUILTIN_VHSDF (TERNOP, fnma, 4, FP)
VAR1 (TERNOP, fnma, 4, FP, hf)
- BUILTIN_VDQF_DF (TERNOP, float_mla, 0, FP)
- BUILTIN_VDQF_DF (TERNOP, float_mls, 0, FP)
- BUILTIN_VDQSF (TERNOP, float_mla_n, 0, FP)
- BUILTIN_VDQSF (TERNOP, float_mls_n, 0, FP)
- BUILTIN_VDQSF (QUADOP_LANE, float_mla_lane, 0, FP)
- BUILTIN_VDQSF (QUADOP_LANE, float_mls_lane, 0, FP)
- BUILTIN_VDQSF (QUADOP_LANE, float_mla_laneq, 0, FP)
- BUILTIN_VDQSF (QUADOP_LANE, float_mls_laneq, 0, FP)
/* Implemented by aarch64_crypto_pmull<mode>. */
VAR1 (BINOPP, crypto_pmull, 0, DEFAULT, di)
VAR1 (BINOPP, crypto_pmull, 0, DEFAULT, v2di)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 11705bc9073..a42e1a60c58 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3059,152 +3059,6 @@ (define_insn "abs<mode>2<vczle><vczbe>"
[(set_attr "type" "neon_fp_abs_<stype><q>")]
)
-(define_expand "aarch64_float_mla<mode>"
- [(set (match_operand:VDQF_DF 0 "register_operand")
- (plus:VDQF_DF
- (mult:VDQF_DF
- (match_operand:VDQF_DF 2 "register_operand")
- (match_operand:VDQF_DF 3 "register_operand"))
- (match_operand:VDQF_DF 1 "register_operand")))]
- "TARGET_SIMD"
- {
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul<mode>3 (scratch, operands[2], operands[3]));
- emit_insn (gen_add<mode>3 (operands[0], operands[1], scratch));
- DONE;
- }
-)
-
-(define_expand "aarch64_float_mls<mode>"
- [(set (match_operand:VDQF_DF 0 "register_operand")
- (minus:VDQF_DF
- (match_operand:VDQF_DF 1 "register_operand")
- (mult:VDQF_DF
- (match_operand:VDQF_DF 2 "register_operand")
- (match_operand:VDQF_DF 3 "register_operand"))))]
- "TARGET_SIMD"
- {
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul<mode>3 (scratch, operands[2], operands[3]));
- emit_insn (gen_sub<mode>3 (operands[0], operands[1], scratch));
- DONE;
- }
-)
-
-(define_expand "aarch64_float_mla_n<mode>"
- [(set (match_operand:VDQSF 0 "register_operand")
- (plus:VDQSF
- (mult:VDQSF
- (vec_duplicate:VDQSF
- (match_operand:<VEL> 3 "register_operand"))
- (match_operand:VDQSF 2 "register_operand"))
- (match_operand:VDQSF 1 "register_operand")))]
- "TARGET_SIMD"
- {
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul_n<mode>3 (scratch, operands[2], operands[3]));
- emit_insn (gen_add<mode>3 (operands[0], operands[1], scratch));
- DONE;
- }
-)
-
-(define_expand "aarch64_float_mls_n<mode>"
- [(set (match_operand:VDQSF 0 "register_operand")
- (minus:VDQSF
- (match_operand:VDQSF 1 "register_operand")
- (mult:VDQSF
- (vec_duplicate:VDQSF
- (match_operand:<VEL> 3 "register_operand"))
- (match_operand:VDQSF 2 "register_operand"))))]
- "TARGET_SIMD"
- {
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul_n<mode>3 (scratch, operands[2], operands[3]));
- emit_insn (gen_sub<mode>3 (operands[0], operands[1], scratch));
- DONE;
- }
-)
-
-(define_expand "aarch64_float_mla_lane<mode>"
- [(set (match_operand:VDQSF 0 "register_operand")
- (plus:VDQSF
- (mult:VDQSF
- (vec_duplicate:VDQSF
- (vec_select:<VEL>
- (match_operand:V2SF 3 "register_operand")
- (parallel [(match_operand:SI 4 "immediate_operand")])))
- (match_operand:VDQSF 2 "register_operand"))
- (match_operand:VDQSF 1 "register_operand")))]
- "TARGET_SIMD"
- {
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul_lane<mode>3 (scratch, operands[2],
- operands[3], operands[4]));
- emit_insn (gen_add<mode>3 (operands[0], operands[1], scratch));
- DONE;
- }
-)
-
-(define_expand "aarch64_float_mls_lane<mode>"
- [(set (match_operand:VDQSF 0 "register_operand")
- (minus:VDQSF
- (match_operand:VDQSF 1 "register_operand")
- (mult:VDQSF
- (vec_duplicate:VDQSF
- (vec_select:<VEL>
- (match_operand:V2SF 3 "register_operand")
- (parallel [(match_operand:SI 4 "immediate_operand")])))
- (match_operand:VDQSF 2 "register_operand"))))]
- "TARGET_SIMD"
- {
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul_lane<mode>3 (scratch, operands[2],
- operands[3], operands[4]));
- emit_insn (gen_sub<mode>3 (operands[0], operands[1], scratch));
- DONE;
- }
-)
-
-(define_expand "aarch64_float_mla_laneq<mode>"
- [(set (match_operand:VDQSF 0 "register_operand")
- (plus:VDQSF
- (mult:VDQSF
- (vec_duplicate:VDQSF
- (vec_select:<VEL>
- (match_operand:V4SF 3 "register_operand")
- (parallel [(match_operand:SI 4 "immediate_operand")])))
- (match_operand:VDQSF 2 "register_operand"))
- (match_operand:VDQSF 1 "register_operand")))]
- "TARGET_SIMD"
- {
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul_laneq<mode>3 (scratch, operands[2],
- operands[3], operands[4]));
- emit_insn (gen_add<mode>3 (operands[0], operands[1], scratch));
- DONE;
- }
-)
-
-(define_expand "aarch64_float_mls_laneq<mode>"
- [(set (match_operand:VDQSF 0 "register_operand")
- (minus:VDQSF
- (match_operand:VDQSF 1 "register_operand")
- (mult:VDQSF
- (vec_duplicate:VDQSF
- (vec_select:<VEL>
- (match_operand:V4SF 3 "register_operand")
- (parallel [(match_operand:SI 4 "immediate_operand")])))
- (match_operand:VDQSF 2 "register_operand"))))]
- "TARGET_SIMD"
- {
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul_laneq<mode>3 (scratch, operands[2],
- operands[3], operands[4]));
- emit_insn (gen_sub<mode>3 (operands[0], operands[1], scratch));
- DONE;
- }
-)
-
(define_insn "fma<mode>4<vczle><vczbe>"
[(set (match_operand:VHSDF 0 "register_operand" "=w")
(fma:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 9caa0a2088d..71b93a6adf5 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -1290,83 +1290,6 @@ vcvtxd_f32_f64 (float64_t __a)
return __builtin_aarch64_float_trunc_rodd_df (__a);
}
-__extension__ extern __inline float32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
-{
- return __builtin_aarch64_float_mla_nv2sf (__a, __b, __c);
-}
-
-__extension__ extern __inline int16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c)
-{
- return __builtin_aarch64_mla_nv4hi (__a, __b, __c);
-}
-
-__extension__ extern __inline int32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c)
-{
- return __builtin_aarch64_mla_nv2si (__a, __b, __c);
-}
-
-__extension__ extern __inline uint16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c)
-{
- return __builtin_aarch64_mla_nv4hi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c)
-{
- return __builtin_aarch64_mla_nv2si_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline int8x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
-{
- return __builtin_aarch64_mlav8qi (__a, __b, __c);
-}
-
-__extension__ extern __inline int16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
-{
- return __builtin_aarch64_mlav4hi (__a, __b, __c);
-}
-
-__extension__ extern __inline int32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
-{
- return __builtin_aarch64_mlav2si (__a, __b, __c);
-}
-
-__extension__ extern __inline uint8x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
-{
- return __builtin_aarch64_mlav8qi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
-{
- return __builtin_aarch64_mlav4hi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
-{
- return __builtin_aarch64_mlav2si_uuuu (__a, __b, __c);
-}
-
__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmlal_high_lane_s16(int32x4_t __a, int16x8_t __b, int16x4_t __v,
@@ -1627,160 +1550,6 @@ vmlal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t
__c)
return __builtin_aarch64_umlalv2si_uuuu (__a, __b, __c);
}
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
-{
- return __builtin_aarch64_float_mla_nv4sf (__a, __b, __c);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c)
-{
- return __builtin_aarch64_mla_nv8hi (__a, __b, __c);
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c)
-{
- return __builtin_aarch64_mla_nv4si (__a, __b, __c);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c)
-{
- return __builtin_aarch64_mla_nv8hi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c)
-{
- return __builtin_aarch64_mla_nv4si_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
-{
- return __builtin_aarch64_mlav16qi (__a, __b, __c);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
-{
- return __builtin_aarch64_mlav8hi (__a, __b, __c);
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
-{
- return __builtin_aarch64_mlav4si (__a, __b, __c);
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
-{
- return __builtin_aarch64_mlav16qi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
-{
- return __builtin_aarch64_mlav8hi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
-{
- return __builtin_aarch64_mlav4si_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline float32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
-{
- return __builtin_aarch64_float_mls_nv2sf (__a, __b, __c);
-}
-
-__extension__ extern __inline int16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c)
-{
- return __builtin_aarch64_mls_nv4hi (__a, __b, __c);
-}
-
-__extension__ extern __inline int32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c)
-{
- return __builtin_aarch64_mls_nv2si (__a, __b, __c);
-}
-
-__extension__ extern __inline uint16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c)
-{
- return __builtin_aarch64_mls_nv4hi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c)
-{
- return __builtin_aarch64_mls_nv2si_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline int8x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
-{
- return __builtin_aarch64_mlsv8qi (__a, __b, __c);
-}
-
-__extension__ extern __inline int16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
-{
- return __builtin_aarch64_mlsv4hi (__a, __b, __c);
-}
-
-__extension__ extern __inline int32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
-{
- return __builtin_aarch64_mlsv2si (__a, __b, __c);
-}
-
-__extension__ extern __inline uint8x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
-{
- return __builtin_aarch64_mlsv8qi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
-{
- return __builtin_aarch64_mlsv4hi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
-{
- return __builtin_aarch64_mlsv2si_uuuu (__a, __b, __c);
-}
-
__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmlsl_high_lane_s16(int32x4_t __a, int16x8_t __b, int16x4_t __v,
@@ -2045,83 +1814,6 @@ vmlsl_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t
__c)
return __builtin_aarch64_umlslv2si_uuuu (__a, __b, __c);
}
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
-{
- return __builtin_aarch64_float_mls_nv4sf (__a, __b, __c);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c)
-{
- return __builtin_aarch64_mls_nv8hi (__a, __b, __c);
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c)
-{
- return __builtin_aarch64_mls_nv4si (__a, __b, __c);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c)
-{
- return __builtin_aarch64_mls_nv8hi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c)
-{
- return __builtin_aarch64_mls_nv4si_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
-{
- return __builtin_aarch64_mlsv16qi (__a, __b, __c);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
-{
- return __builtin_aarch64_mlsv8hi (__a, __b, __c);
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
-{
- return __builtin_aarch64_mlsv4si (__a, __b, __c);
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
-{
- return __builtin_aarch64_mlsv16qi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
-{
- return __builtin_aarch64_mlsv8hi_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
-{
- return __builtin_aarch64_mlsv4si_uuuu (__a, __b, __c);
-}
-
__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmovl_high_s8 (int8x16_t __a)
@@ -11405,399 +11097,69 @@ vminvq_f64 (float64x2_t __a)
return __builtin_aarch64_reduc_smin_nan_scal_v2df (__a);
}
-/* vmla */
-
-__extension__ extern __inline float32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
-{
- return __builtin_aarch64_float_mlav2sf (__a, __b, __c);
-}
-
-__extension__ extern __inline float64x1_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
-{
- return (float64x1_t) {__builtin_aarch64_float_mladf (__a[0], __b[0],
__c[0])};
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
-{
- return __builtin_aarch64_float_mlav4sf (__a, __b, __c);
-}
-
-__extension__ extern __inline float64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
-{
- return __builtin_aarch64_float_mlav2df (__a, __b, __c);
-}
-
-/* vmla_lane */
-
-__extension__ extern __inline float32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_lane_f32 (float32x2_t __a, float32x2_t __b,
- float32x2_t __c, const int __lane)
-{
- return __builtin_aarch64_float_mla_lanev2sf (__a, __b, __c, __lane);
-}
-
-__extension__ extern __inline int16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_lane_s16 (int16x4_t __a, int16x4_t __b,
- int16x4_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline int32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_lane_s32 (int32x2_t __a, int32x2_t __b,
- int32x2_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_lane_u16 (uint16x4_t __a, uint16x4_t __b,
- uint16x4_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_lane_u32 (uint32x2_t __a, uint32x2_t __b,
- uint32x2_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-/* vmla_laneq */
-
-__extension__ extern __inline float32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_laneq_f32 (float32x2_t __a, float32x2_t __b,
- float32x4_t __c, const int __lane)
-{
- return __builtin_aarch64_float_mla_laneqv2sf (__a, __b, __c, __lane);
-}
-
-__extension__ extern __inline int16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_laneq_s16 (int16x4_t __a, int16x4_t __b,
- int16x8_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline int32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_laneq_s32 (int32x2_t __a, int32x2_t __b,
- int32x4_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
- uint16x8_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmla_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
- uint32x4_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-/* vmlaq_lane */
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_lane_f32 (float32x4_t __a, float32x4_t __b,
- float32x2_t __c, const int __lane)
-{
- return __builtin_aarch64_float_mla_lanev4sf (__a, __b, __c, __lane);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_lane_s16 (int16x8_t __a, int16x8_t __b,
- int16x4_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_lane_s32 (int32x4_t __a, int32x4_t __b,
- int32x2_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
- uint16x4_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
- uint32x2_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
- /* vmlaq_laneq */
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
- float32x4_t __c, const int __lane)
-{
- return __builtin_aarch64_float_mla_laneqv4sf (__a, __b, __c, __lane);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_laneq_s16 (int16x8_t __a, int16x8_t __b,
- int16x8_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_laneq_s32 (int32x4_t __a, int32x4_t __b,
- int32x4_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
- uint16x8_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlaq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
- uint32x4_t __c, const int __lane)
-{
- return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-/* vmls */
-
-__extension__ extern __inline float32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
-{
- return __builtin_aarch64_float_mlsv2sf (__a, __b, __c);
-}
-
-__extension__ extern __inline float64x1_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
-{
- return (float64x1_t) {__builtin_aarch64_float_mlsdf (__a[0], __b[0],
__c[0])};
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
-{
- return __builtin_aarch64_float_mlsv4sf (__a, __b, __c);
-}
-
-__extension__ extern __inline float64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
-{
- return __builtin_aarch64_float_mlsv2df (__a, __b, __c);
-}
-
-/* vmls_lane */
-
-__extension__ extern __inline float32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_lane_f32 (float32x2_t __a, float32x2_t __b,
- float32x2_t __c, const int __lane)
-{
- return __builtin_aarch64_float_mls_lanev2sf (__a, __b, __c, __lane);
-}
-
-__extension__ extern __inline int16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_lane_s16 (int16x4_t __a, int16x4_t __b,
- int16x4_t __c, const int __lane)
-{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline int32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_lane_s32 (int32x2_t __a, int32x2_t __b,
- int32x2_t __c, const int __lane)
-{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_lane_u16 (uint16x4_t __a, uint16x4_t __b,
- uint16x4_t __c, const int __lane)
-{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_lane_u32 (uint32x2_t __a, uint32x2_t __b,
- uint32x2_t __c, const int __lane)
-{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-/* vmls_laneq */
-
-__extension__ extern __inline float32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_laneq_f32 (float32x2_t __a, float32x2_t __b,
- float32x4_t __c, const int __lane)
-{
- return __builtin_aarch64_float_mls_laneqv2sf (__a, __b, __c, __lane);
-}
-
-__extension__ extern __inline int16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_laneq_s16 (int16x4_t __a, int16x4_t __b,
- int16x8_t __c, const int __lane)
-{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline int32x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_laneq_s32 (int32x2_t __a, int32x2_t __b,
- int32x4_t __c, const int __lane)
-{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint16x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
- uint16x8_t __c, const int __lane)
-{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-
-__extension__ extern __inline uint32x2_t
+__extension__ extern __inline int8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmls_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
- uint32x4_t __c, const int __lane)
+vminvq_s8 (int8x16_t __a)
{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ return __builtin_aarch64_reduc_smin_scal_v16qi (__a);
}
-/* vmlsq_lane */
-
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_lane_f32 (float32x4_t __a, float32x4_t __b,
- float32x2_t __c, const int __lane)
+vminvq_s16 (int16x8_t __a)
{
- return __builtin_aarch64_float_mls_lanev4sf (__a, __b, __c, __lane);
+ return __builtin_aarch64_reduc_smin_scal_v8hi (__a);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline int32_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_lane_s16 (int16x8_t __a, int16x8_t __b,
- int16x4_t __c, const int __lane)
+vminvq_s32 (int32x4_t __a)
{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ return __builtin_aarch64_reduc_smin_scal_v4si (__a);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline uint8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_lane_s32 (int32x4_t __a, int32x4_t __b,
- int32x2_t __c, const int __lane)
+vminvq_u8 (uint8x16_t __a)
{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ return __builtin_aarch64_reduc_umin_scal_v16qi_uu (__a);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline uint16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
- uint16x4_t __c, const int __lane)
+vminvq_u16 (uint16x8_t __a)
{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ return __builtin_aarch64_reduc_umin_scal_v8hi_uu (__a);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline uint32_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
- uint32x2_t __c, const int __lane)
+vminvq_u32 (uint32x4_t __a)
{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ return __builtin_aarch64_reduc_umin_scal_v4si_uu (__a);
}
- /* vmlsq_laneq */
+/* vminnmv */
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
- float32x4_t __c, const int __lane)
-{
- return __builtin_aarch64_float_mls_laneqv4sf (__a, __b, __c, __lane);
-}
-
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline float32_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_laneq_s16 (int16x8_t __a, int16x8_t __b,
- int16x8_t __c, const int __lane)
+vminnmv_f32 (float32x2_t __a)
{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ return __builtin_aarch64_reduc_smin_scal_v2sf (__a);
}
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_laneq_s32 (int32x4_t __a, int32x4_t __b,
- int32x4_t __c, const int __lane)
-{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
-}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline float32_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
- uint16x8_t __c, const int __lane)
+vminnmvq_f32 (float32x4_t __a)
{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ return __builtin_aarch64_reduc_smin_scal_v4sf (__a);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline float64_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmlsq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
- uint32x4_t __c, const int __lane)
+vminnmvq_f64 (float64x2_t __a)
{
- return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ return __builtin_aarch64_reduc_smin_scal_v2df (__a);
}
/* vpadd */
diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vmla.c
b/gcc/testsuite/gcc.target/aarch64/neon/vmla.c
new file mode 100644
index 00000000000..a247987b1fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/neon/vmla.c
@@ -0,0 +1,350 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_neon_test.h"
+
+#define TEST_LANE(NAME, RET_TYPE, TYPE1, TYPE2, TYPE3)
\
+ RET_TYPE test_##NAME (TYPE1 a, TYPE2 b, TYPE3 c)
\
+ {
\
+ return NAME (a, b, c, VEC_LEN (c) - 1);
\
+ }
+
+/*
+** test_vmla_s8:
+** mla v0\.8b, (v1\.8b, v2\.8b|v2\.8b, v1\.8b)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmla_s8, int8x8_t)
+
+/*
+** test_vmla_u8:
+** mla v0\.8b, (v1\.8b, v2\.8b|v2\.8b, v1\.8b)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmla_u8, uint8x8_t)
+
+/*
+** test_vmlaq_s8:
+** mla v0\.16b, (v1\.16b, v2\.16b|v2\.16b, v1\.16b)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlaq_s8, int8x16_t)
+
+/*
+** test_vmlaq_u8:
+** mla v0\.16b, (v1\.16b, v2\.16b|v2\.16b, v1\.16b)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlaq_u8, uint8x16_t)
+
+/*
+** test_vmla_s16:
+** mla v0\.4h, (v1\.4h, v2\.4h|v2\.4h, v1\.4h)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmla_s16, int16x4_t)
+
+/*
+** test_vmla_u16:
+** mla v0\.4h, (v1\.4h, v2\.4h|v2\.4h, v1\.4h)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmla_u16, uint16x4_t)
+
+/*
+** test_vmlaq_s16:
+** mla v0\.8h, (v1\.8h, v2\.8h|v2\.8h, v1\.8h)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlaq_s16, int16x8_t)
+
+/*
+** test_vmlaq_u16:
+** mla v0\.8h, (v1\.8h, v2\.8h|v2\.8h, v1\.8h)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlaq_u16, uint16x8_t)
+
+/*
+** test_vmla_s32:
+** mla v0\.2s, (v1\.2s, v2\.2s|v2\.2s, v1\.2s)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmla_s32, int32x2_t)
+
+/*
+** test_vmla_u32:
+** mla v0\.2s, (v1\.2s, v2\.2s|v2\.2s, v1\.2s)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmla_u32, uint32x2_t)
+
+/*
+** test_vmlaq_s32:
+** mla v0\.4s, (v1\.4s, v2\.4s|v2\.4s, v1\.4s)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlaq_s32, int32x4_t)
+
+/*
+** test_vmlaq_u32:
+** mla v0\.4s, (v1\.4s, v2\.4s|v2\.4s, v1\.4s)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlaq_u32, uint32x4_t)
+
+/*
+** test_vmla_f32:
+** fmul (v[0-9]+\.2s), (v1\.2s, v2\.2s|v2\.2s, v1\.2s)
+** fadd v0\.2s, (\1, v0\.2s|v0\.2s, \1)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmla_f32, float32x2_t)
+
+/*
+** test_vmlaq_f32:
+** fmul (v[0-9]+\.4s), (v1\.4s, v2\.4s|v2\.4s, v1\.4s)
+** fadd v0\.4s, (\1, v0\.4s|v0\.4s, \1)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlaq_f32, float32x4_t)
+
+/*
+** test_vmla_f64:
+** fmul (d[0-9]+), (d1, d2|d2, d1)
+** fadd d0, (\1, d0|d0, \1)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmla_f64, float64x1_t)
+
+/*
+** test_vmlaq_f64:
+** fmul (v[0-9]+\.2d), (v1\.2d, v2\.2d|v2\.2d, v1\.2d)
+** fadd v0\.2d, (\1, v0\.2d|v0\.2d, \1)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlaq_f64, float64x2_t)
+
+/*
+** test_vmla_n_s16:
+** dup v([0-9]+)\.4h, w0
+** mla v0\.4h, v1\.4h, v\1\.h\[0\]
+** ret
+*/
+TEST_TERNARY (vmla_n_s16, int16x4_t, int16x4_t, int16x4_t, int16_t)
+
+/*
+** test_vmla_n_u16:
+** dup v([0-9]+)\.4h, w0
+** mla v0\.4h, v1\.4h, v\1\.h\[0\]
+** ret
+*/
+TEST_TERNARY (vmla_n_u16, uint16x4_t, uint16x4_t, uint16x4_t, uint16_t)
+
+/*
+** test_vmlaq_n_s16:
+** dup v([0-9]+)\.4h, w0
+** mla v0\.8h, v1\.8h, v\1\.h\[0\]
+** ret
+*/
+TEST_TERNARY (vmlaq_n_s16, int16x8_t, int16x8_t, int16x8_t, int16_t)
+
+/*
+** test_vmlaq_n_u16:
+** dup v([0-9]+)\.4h, w0
+** mla v0\.8h, v1\.8h, v\1\.h\[0\]
+** ret
+*/
+TEST_TERNARY (vmlaq_n_u16, uint16x8_t, uint16x8_t, uint16x8_t, uint16_t)
+
+/*
+** test_vmla_n_s32:
+** fmov s([0-9]+), w0
+** mla v0\.2s, v1\.2s, v\1\.s\[0\]
+** ret
+*/
+TEST_TERNARY (vmla_n_s32, int32x2_t, int32x2_t, int32x2_t, int32_t)
+
+/*
+** test_vmla_n_u32:
+** fmov s([0-9]+), w0
+** mla v0\.2s, v1\.2s, v\1\.s\[0\]
+** ret
+*/
+TEST_TERNARY (vmla_n_u32, uint32x2_t, uint32x2_t, uint32x2_t, uint32_t)
+
+/*
+** test_vmlaq_n_s32:
+** fmov s([0-9]+), w0
+** mla v0\.4s, v1\.4s, v\1\.s\[0\]
+** ret
+*/
+TEST_TERNARY (vmlaq_n_s32, int32x4_t, int32x4_t, int32x4_t, int32_t)
+
+/*
+** test_vmlaq_n_u32:
+** fmov s([0-9]+), w0
+** mla v0\.4s, v1\.4s, v\1\.s\[0\]
+** ret
+*/
+TEST_TERNARY (vmlaq_n_u32, uint32x4_t, uint32x4_t, uint32x4_t, uint32_t)
+
+/*
+** test_vmla_n_f32:
+** fmul (v[0-9]+\.2s), v1\.2s, v2\.s\[0\]
+** fadd v0\.2s, (\1, v0\.2s|v0\.2s, \1)
+** ret
+*/
+TEST_TERNARY (vmla_n_f32, float32x2_t, float32x2_t, float32x2_t, float32_t)
+
+/*
+** test_vmlaq_n_f32:
+** fmul (v[0-9]+\.4s), v1\.4s, v2\.s\[0\]
+** fadd v0\.4s, (\1, v0\.4s|v0\.4s, \1)
+** ret
+*/
+TEST_TERNARY (vmlaq_n_f32, float32x4_t, float32x4_t, float32x4_t, float32_t)
+
+/*
+** test_vmla_lane_s16:
+** mla v0\.4h, v1\.4h, v2\.h\[3\]
+** ret
+*/
+TEST_LANE (vmla_lane_s16, int16x4_t, int16x4_t, int16x4_t, int16x4_t)
+
+/*
+** test_vmla_lane_u16:
+** mla v0\.4h, v1\.4h, v2\.h\[3\]
+** ret
+*/
+TEST_LANE (vmla_lane_u16, uint16x4_t, uint16x4_t, uint16x4_t, uint16x4_t)
+
+/*
+** test_vmla_lane_s32:
+** mla v0\.2s, v1\.2s, v2\.s\[1\]
+** ret
+*/
+TEST_LANE (vmla_lane_s32, int32x2_t, int32x2_t, int32x2_t, int32x2_t)
+
+/*
+** test_vmla_lane_u32:
+** mla v0\.2s, v1\.2s, v2\.s\[1\]
+** ret
+*/
+TEST_LANE (vmla_lane_u32, uint32x2_t, uint32x2_t, uint32x2_t, uint32x2_t)
+
+/*
+** test_vmla_lane_f32:
+** fmul (v[0-9]+\.2s), v1\.2s, v2\.s\[1\]
+** fadd v0\.2s, (\1, v0\.2s|v0\.2s, \1)
+** ret
+*/
+TEST_LANE (vmla_lane_f32, float32x2_t, float32x2_t, float32x2_t, float32x2_t)
+
+/*
+** test_vmla_laneq_s16:
+** mla v0\.4h, v1\.4h, v2\.h\[7\]
+** ret
+*/
+TEST_LANE (vmla_laneq_s16, int16x4_t, int16x4_t, int16x4_t, int16x8_t)
+
+/*
+** test_vmla_laneq_u16:
+** mla v0\.4h, v1\.4h, v2\.h\[7\]
+** ret
+*/
+TEST_LANE (vmla_laneq_u16, uint16x4_t, uint16x4_t, uint16x4_t, uint16x8_t)
+
+/*
+** test_vmla_laneq_s32:
+** mla v0\.2s, v1\.2s, v2\.s\[3\]
+** ret
+*/
+TEST_LANE (vmla_laneq_s32, int32x2_t, int32x2_t, int32x2_t, int32x4_t)
+
+/*
+** test_vmla_laneq_u32:
+** mla v0\.2s, v1\.2s, v2\.s\[3\]
+** ret
+*/
+TEST_LANE (vmla_laneq_u32, uint32x2_t, uint32x2_t, uint32x2_t, uint32x4_t)
+
+/*
+** test_vmla_laneq_f32:
+** fmul (v[0-9]+\.2s), v1\.2s, v2\.s\[3\]
+** fadd v0\.2s, (\1, v0\.2s|v0\.2s, \1)
+** ret
+*/
+TEST_LANE (vmla_laneq_f32, float32x2_t, float32x2_t, float32x2_t, float32x4_t)
+
+/*
+** test_vmlaq_lane_s16:
+** mla v0\.8h, v1\.8h, v2\.h\[3\]
+** ret
+*/
+TEST_LANE (vmlaq_lane_s16, int16x8_t, int16x8_t, int16x8_t, int16x4_t)
+
+/*
+** test_vmlaq_lane_u16:
+** mla v0\.8h, v1\.8h, v2\.h\[3\]
+** ret
+*/
+TEST_LANE (vmlaq_lane_u16, uint16x8_t, uint16x8_t, uint16x8_t, uint16x4_t)
+
+/*
+** test_vmlaq_lane_s32:
+** mla v0\.4s, v1\.4s, v2\.s\[1\]
+** ret
+*/
+TEST_LANE (vmlaq_lane_s32, int32x4_t, int32x4_t, int32x4_t, int32x2_t)
+
+/*
+** test_vmlaq_lane_u32:
+** mla v0\.4s, v1\.4s, v2\.s\[1\]
+** ret
+*/
+TEST_LANE (vmlaq_lane_u32, uint32x4_t, uint32x4_t, uint32x4_t, uint32x2_t)
+
+/*
+** test_vmlaq_lane_f32:
+** fmul (v[0-9]+\.4s), v1\.4s, v2\.s\[1\]
+** fadd v0\.4s, (\1, v0\.4s|v0\.4s, \1)
+** ret
+*/
+TEST_LANE (vmlaq_lane_f32, float32x4_t, float32x4_t, float32x4_t, float32x2_t)
+
+/*
+** test_vmlaq_laneq_s16:
+** mla v0\.8h, v1\.8h, v2\.h\[7\]
+** ret
+*/
+TEST_LANE (vmlaq_laneq_s16, int16x8_t, int16x8_t, int16x8_t, int16x8_t)
+
+/*
+** test_vmlaq_laneq_u16:
+** mla v0\.8h, v1\.8h, v2\.h\[7\]
+** ret
+*/
+TEST_LANE (vmlaq_laneq_u16, uint16x8_t, uint16x8_t, uint16x8_t, uint16x8_t)
+
+/*
+** test_vmlaq_laneq_s32:
+** mla v0\.4s, v1\.4s, v2\.s\[3\]
+** ret
+*/
+TEST_LANE (vmlaq_laneq_s32, int32x4_t, int32x4_t, int32x4_t, int32x4_t)
+
+/*
+** test_vmlaq_laneq_u32:
+** mla v0\.4s, v1\.4s, v2\.s\[3\]
+** ret
+*/
+TEST_LANE (vmlaq_laneq_u32, uint32x4_t, uint32x4_t, uint32x4_t, uint32x4_t)
+
+/*
+** test_vmlaq_laneq_f32:
+** fmul (v[0-9]+\.4s), v1\.4s, v2\.s\[3\]
+** fadd v0\.4s, (\1, v0\.4s|v0\.4s, \1)
+** ret
+*/
+TEST_LANE (vmlaq_laneq_f32, float32x4_t, float32x4_t, float32x4_t, float32x4_t)
diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vmls.c
b/gcc/testsuite/gcc.target/aarch64/neon/vmls.c
new file mode 100644
index 00000000000..cb851681b18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/neon/vmls.c
@@ -0,0 +1,350 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_neon_test.h"
+
+#define TEST_LANE(NAME, RET_TYPE, TYPE1, TYPE2, TYPE3)
\
+ RET_TYPE test_##NAME (TYPE1 a, TYPE2 b, TYPE3 c)
\
+ {
\
+ return NAME (a, b, c, VEC_LEN (c) - 1);
\
+ }
+
+/*
+** test_vmls_s8:
+** mls v0\.8b, (v1\.8b, v2\.8b|v2\.8b, v1\.8b)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmls_s8, int8x8_t)
+
+/*
+** test_vmls_u8:
+** mls v0\.8b, (v1\.8b, v2\.8b|v2\.8b, v1\.8b)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmls_u8, uint8x8_t)
+
+/*
+** test_vmlsq_s8:
+** mls v0\.16b, (v1\.16b, v2\.16b|v2\.16b, v1\.16b)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlsq_s8, int8x16_t)
+
+/*
+** test_vmlsq_u8:
+** mls v0\.16b, (v1\.16b, v2\.16b|v2\.16b, v1\.16b)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlsq_u8, uint8x16_t)
+
+/*
+** test_vmls_s16:
+** mls v0\.4h, (v1\.4h, v2\.4h|v2\.4h, v1\.4h)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmls_s16, int16x4_t)
+
+/*
+** test_vmls_u16:
+** mls v0\.4h, (v1\.4h, v2\.4h|v2\.4h, v1\.4h)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmls_u16, uint16x4_t)
+
+/*
+** test_vmlsq_s16:
+** mls v0\.8h, (v1\.8h, v2\.8h|v2\.8h, v1\.8h)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlsq_s16, int16x8_t)
+
+/*
+** test_vmlsq_u16:
+** mls v0\.8h, (v1\.8h, v2\.8h|v2\.8h, v1\.8h)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlsq_u16, uint16x8_t)
+
+/*
+** test_vmls_s32:
+** mls v0\.2s, (v1\.2s, v2\.2s|v2\.2s, v1\.2s)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmls_s32, int32x2_t)
+
+/*
+** test_vmls_u32:
+** mls v0\.2s, (v1\.2s, v2\.2s|v2\.2s, v1\.2s)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmls_u32, uint32x2_t)
+
+/*
+** test_vmlsq_s32:
+** mls v0\.4s, (v1\.4s, v2\.4s|v2\.4s, v1\.4s)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlsq_s32, int32x4_t)
+
+/*
+** test_vmlsq_u32:
+** mls v0\.4s, (v1\.4s, v2\.4s|v2\.4s, v1\.4s)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlsq_u32, uint32x4_t)
+
+/*
+** test_vmls_f32:
+** fmul (v[0-9]+\.2s), (v1\.2s, v2\.2s|v2\.2s, v1\.2s)
+** fsub v0\.2s, (\1, v0\.2s|v0\.2s, \1)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmls_f32, float32x2_t)
+
+/*
+** test_vmlsq_f32:
+** fmul (v[0-9]+\.4s), (v1\.4s, v2\.4s|v2\.4s, v1\.4s)
+** fsub v0\.4s, (\1, v0\.4s|v0\.4s, \1)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlsq_f32, float32x4_t)
+
+/*
+** test_vmls_f64:
+** fmul (d[0-9]+), (d1, d2|d2, d1)
+** fsub d0, (\1, d0|d0, \1)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmls_f64, float64x1_t)
+
+/*
+** test_vmlsq_f64:
+** fmul (v[0-9]+\.2d), (v1\.2d, v2\.2d|v2\.2d, v1\.2d)
+** fsub v0\.2d, (\1, v0\.2d|v0\.2d, \1)
+** ret
+*/
+TEST_UNIFORM_TERNARY (vmlsq_f64, float64x2_t)
+
+/*
+** test_vmls_n_s16:
+** dup v([0-9]+)\.4h, w0
+** mls v0\.4h, v1\.4h, v\1\.h\[0\]
+** ret
+*/
+TEST_TERNARY (vmls_n_s16, int16x4_t, int16x4_t, int16x4_t, int16_t)
+
+/*
+** test_vmls_n_u16:
+** dup v([0-9]+)\.4h, w0
+** mls v0\.4h, v1\.4h, v\1\.h\[0\]
+** ret
+*/
+TEST_TERNARY (vmls_n_u16, uint16x4_t, uint16x4_t, uint16x4_t, uint16_t)
+
+/*
+** test_vmlsq_n_s16:
+** dup v([0-9]+)\.4h, w0
+** mls v0\.8h, v1\.8h, v\1\.h\[0\]
+** ret
+*/
+TEST_TERNARY (vmlsq_n_s16, int16x8_t, int16x8_t, int16x8_t, int16_t)
+
+/*
+** test_vmlsq_n_u16:
+** dup v([0-9]+)\.4h, w0
+** mls v0\.8h, v1\.8h, v\1\.h\[0\]
+** ret
+*/
+TEST_TERNARY (vmlsq_n_u16, uint16x8_t, uint16x8_t, uint16x8_t, uint16_t)
+
+/*
+** test_vmls_n_s32:
+** fmov s([0-9]+), w0
+** mls v0\.2s, v1\.2s, v\1\.s\[0\]
+** ret
+*/
+TEST_TERNARY (vmls_n_s32, int32x2_t, int32x2_t, int32x2_t, int32_t)
+
+/*
+** test_vmls_n_u32:
+** fmov s([0-9]+), w0
+** mls v0\.2s, v1\.2s, v\1\.s\[0\]
+** ret
+*/
+TEST_TERNARY (vmls_n_u32, uint32x2_t, uint32x2_t, uint32x2_t, uint32_t)
+
+/*
+** test_vmlsq_n_s32:
+** fmov s([0-9]+), w0
+** mls v0\.4s, v1\.4s, v\1\.s\[0\]
+** ret
+*/
+TEST_TERNARY (vmlsq_n_s32, int32x4_t, int32x4_t, int32x4_t, int32_t)
+
+/*
+** test_vmlsq_n_u32:
+** fmov s([0-9]+), w0
+** mls v0\.4s, v1\.4s, v\1\.s\[0\]
+** ret
+*/
+TEST_TERNARY (vmlsq_n_u32, uint32x4_t, uint32x4_t, uint32x4_t, uint32_t)
+
+/*
+** test_vmls_n_f32:
+** fmul (v[0-9]+\.2s), v1\.2s, v2\.s\[0\]
+** fsub v0\.2s, (\1, v0\.2s|v0\.2s, \1)
+** ret
+*/
+TEST_TERNARY (vmls_n_f32, float32x2_t, float32x2_t, float32x2_t, float32_t)
+
+/*
+** test_vmlsq_n_f32:
+** fmul (v[0-9]+\.4s), v1\.4s, v2\.s\[0\]
+** fsub v0\.4s, (\1, v0\.4s|v0\.4s, \1)
+** ret
+*/
+TEST_TERNARY (vmlsq_n_f32, float32x4_t, float32x4_t, float32x4_t, float32_t)
+
+/*
+** test_vmls_lane_s16:
+** mls v0\.4h, v1\.4h, v2\.h\[3\]
+** ret
+*/
+TEST_LANE (vmls_lane_s16, int16x4_t, int16x4_t, int16x4_t, int16x4_t)
+
+/*
+** test_vmls_lane_u16:
+** mls v0\.4h, v1\.4h, v2\.h\[3\]
+** ret
+*/
+TEST_LANE (vmls_lane_u16, uint16x4_t, uint16x4_t, uint16x4_t, uint16x4_t)
+
+/*
+** test_vmls_lane_s32:
+** mls v0\.2s, v1\.2s, v2\.s\[1\]
+** ret
+*/
+TEST_LANE (vmls_lane_s32, int32x2_t, int32x2_t, int32x2_t, int32x2_t)
+
+/*
+** test_vmls_lane_u32:
+** mls v0\.2s, v1\.2s, v2\.s\[1\]
+** ret
+*/
+TEST_LANE (vmls_lane_u32, uint32x2_t, uint32x2_t, uint32x2_t, uint32x2_t)
+
+/*
+** test_vmls_lane_f32:
+** fmul (v[0-9]+\.2s), v1\.2s, v2\.s\[1\]
+** fsub v0\.2s, (\1, v0\.2s|v0\.2s, \1)
+** ret
+*/
+TEST_LANE (vmls_lane_f32, float32x2_t, float32x2_t, float32x2_t, float32x2_t)
+
+/*
+** test_vmls_laneq_s16:
+** mls v0\.4h, v1\.4h, v2\.h\[7\]
+** ret
+*/
+TEST_LANE (vmls_laneq_s16, int16x4_t, int16x4_t, int16x4_t, int16x8_t)
+
+/*
+** test_vmls_laneq_u16:
+** mls v0\.4h, v1\.4h, v2\.h\[7\]
+** ret
+*/
+TEST_LANE (vmls_laneq_u16, uint16x4_t, uint16x4_t, uint16x4_t, uint16x8_t)
+
+/*
+** test_vmls_laneq_s32:
+** mls v0\.2s, v1\.2s, v2\.s\[3\]
+** ret
+*/
+TEST_LANE (vmls_laneq_s32, int32x2_t, int32x2_t, int32x2_t, int32x4_t)
+
+/*
+** test_vmls_laneq_u32:
+** mls v0\.2s, v1\.2s, v2\.s\[3\]
+** ret
+*/
+TEST_LANE (vmls_laneq_u32, uint32x2_t, uint32x2_t, uint32x2_t, uint32x4_t)
+
+/*
+** test_vmls_laneq_f32:
+** fmul (v[0-9]+\.2s), v1\.2s, v2\.s\[3\]
+** fsub v0\.2s, (\1, v0\.2s|v0\.2s, \1)
+** ret
+*/
+TEST_LANE (vmls_laneq_f32, float32x2_t, float32x2_t, float32x2_t, float32x4_t)
+
+/*
+** test_vmlsq_lane_s16:
+** mls v0\.8h, v1\.8h, v2\.h\[3\]
+** ret
+*/
+TEST_LANE (vmlsq_lane_s16, int16x8_t, int16x8_t, int16x8_t, int16x4_t)
+
+/*
+** test_vmlsq_lane_u16:
+** mls v0\.8h, v1\.8h, v2\.h\[3\]
+** ret
+*/
+TEST_LANE (vmlsq_lane_u16, uint16x8_t, uint16x8_t, uint16x8_t, uint16x4_t)
+
+/*
+** test_vmlsq_lane_s32:
+** mls v0\.4s, v1\.4s, v2\.s\[1\]
+** ret
+*/
+TEST_LANE (vmlsq_lane_s32, int32x4_t, int32x4_t, int32x4_t, int32x2_t)
+
+/*
+** test_vmlsq_lane_u32:
+** mls v0\.4s, v1\.4s, v2\.s\[1\]
+** ret
+*/
+TEST_LANE (vmlsq_lane_u32, uint32x4_t, uint32x4_t, uint32x4_t, uint32x2_t)
+
+/*
+** test_vmlsq_lane_f32:
+** fmul (v[0-9]+\.4s), v1\.4s, v2\.s\[1\]
+** fsub v0\.4s, (\1, v0\.4s|v0\.4s, \1)
+** ret
+*/
+TEST_LANE (vmlsq_lane_f32, float32x4_t, float32x4_t, float32x4_t, float32x2_t)
+
+/*
+** test_vmlsq_laneq_s16:
+** mls v0\.8h, v1\.8h, v2\.h\[7\]
+** ret
+*/
+TEST_LANE (vmlsq_laneq_s16, int16x8_t, int16x8_t, int16x8_t, int16x8_t)
+
+/*
+** test_vmlsq_laneq_u16:
+** mls v0\.8h, v1\.8h, v2\.h\[7\]
+** ret
+*/
+TEST_LANE (vmlsq_laneq_u16, uint16x8_t, uint16x8_t, uint16x8_t, uint16x8_t)
+
+/*
+** test_vmlsq_laneq_s32:
+** mls v0\.4s, v1\.4s, v2\.s\[3\]
+** ret
+*/
+TEST_LANE (vmlsq_laneq_s32, int32x4_t, int32x4_t, int32x4_t, int32x4_t)
+
+/*
+** test_vmlsq_laneq_u32:
+** mls v0\.4s, v1\.4s, v2\.s\[3\]
+** ret
+*/
+TEST_LANE (vmlsq_laneq_u32, uint32x4_t, uint32x4_t, uint32x4_t, uint32x4_t)
+
+/*
+** test_vmlsq_laneq_f32:
+** fmul (v[0-9]+\.4s), v1\.4s, v2\.s\[3\]
+** fsub v0\.4s, (\1, v0\.4s|v0\.4s, \1)
+** ret
+*/
+TEST_LANE (vmlsq_laneq_f32, float32x4_t, float32x4_t, float32x4_t, float32x4_t)
--
2.56.0
