From: Trevor Saunders <[email protected]>
gen_<name> still returns the pattern, or an rtx_insn * when the expand
emits a sequence. gen_insn_<name> builds the uninserted insn with
make_*_insn_raw.
This originally started with trying to return rtx_insn * from gen_*
only when it was generating a sequence of instructions so would be a
trivial return type change. However since plenty of target code
interchanges function pointers to gen_foo that generates a sequence with
one that only generates a pattern, I ended up creating a new set of
gen_insn_foo as well that returns the same sequence, or for a pattern
also generates the appropriate insn/call_insn/jump_insn wrapper for it,
that ay gen_insn_foo consistently returns rtx_insn * in a state that can
be passed to emit_*. ultimately I tend to think it may make sense to
switch more to the gen_insn_foo form on the theory its slightly faster
if the insn type is statically computed rather than emit_* calling
classify_insn at compile time. However I'm not sure if there is
general agreement with that direction, or other ideas? As can be seen in
the s390.cc changes this removes a few as_a casts and once more fully
converted to gen_insn_* helps more with that?
bootstrapped and regtested on ppc64le-linux-gnu, and run through
config-list.mk with the following patch, ok?
Thanks
Trev
gcc/ChangeLog:
* emit-rtl.cc (make_insn_raw, make_debug_insn_raw,
make_jump_insn_raw, make_call_insn_raw): Clear the next and
previous links. Export the jump and call makers.
* genemit.cc (start_gen_insn): Take return_pat.
(gen_insn_wrapper): New function.
(gen_insn, gen_expand): Emit a gen_insn_NAME wrapper.
* genflags.cc (gen_proto): Declare gen_insn_NAME, stub an elided
pattern, and return rtx_insn * from a sequence expand.
* gensupport.cc (get_make_insn_function): Rename from
get_emit_function. Return make_*_insn_raw.
* gensupport.h (get_make_insn_function): Declare.
* rtl.cc (classify_insn_vec, predicate_is_always_insn): New
functions.
(classify_insn): Classify PARALLEL and MATCH_PARALLEL from their
elements. Treat a const_int match_operand as an insn.
* rtl.h (make_jump_insn_raw, make_call_insn_raw): Declare.
* config/i386/i386-expand.cc: Use an rtx_insn * generator.
* config/aarch64/aarch64-builtins.cc
(aarch64_expand_builtin_rsqrt): Use an rtx_insn * generator.
* config/arm/arm.cc (arm_block_set_unaligned_vect): Likewise.
* config/avr/avr-passes.cc: Likewise.
* config/avr/avr-protos.h (avr_emit3_fix_outputs): Likewise.
* config/avr/avr.cc (avr_emit3_fix_outputs): Likewise.
* config/i386/i386-protos.h (ix86_expand_reduc): Likewise.
* config/i386/i386.md: Likewise.
* config/i386/mmx.md: Likewise.
* config/i386/sse.md: Likewise.
* config/i386/sync.md: Likewise.
* config/ia64/ia64.cc: Likewise.
* config/loongarch/lasx.md: Likewise.
* config/loongarch/loongarch-protos.h: Likewise.
* config/loongarch/loongarch.cc: Likewise.
* config/mips/loongson-mmi.md: Likewise.
* config/mips/mips-protos.h: Likewise.
* config/mips/mips.cc: Likewise.
* config/rl78/rl78-protos.h: Likewise.
* config/rl78/rl78.cc: Likewise.
* config/rs6000/rs6000-string.cc: Likewise.
* config/rs6000/rs6000.cc: Likewise.
Signed-off-by: Trevor Saunders <[email protected]>
---
gcc/config/aarch64/aarch64-builtins.cc | 2 +-
gcc/config/arm/arm.cc | 2 +-
gcc/config/avr/avr-passes.cc | 5 +-
gcc/config/avr/avr-protos.h | 3 +-
gcc/config/avr/avr.cc | 2 +-
gcc/config/i386/i386-expand.cc | 150 ++++++++++++------------
gcc/config/i386/i386-protos.h | 2 +-
gcc/config/i386/i386.md | 14 +--
gcc/config/i386/mmx.md | 14 +--
gcc/config/i386/sse.md | 78 ++++++------
gcc/config/i386/sync.md | 6 +-
gcc/config/ia64/ia64.cc | 27 +++--
gcc/config/loongarch/lasx.md | 8 +-
gcc/config/loongarch/loongarch-protos.h | 2 +-
gcc/config/loongarch/loongarch.cc | 7 +-
gcc/config/mips/loongson-mmi.md | 10 +-
gcc/config/mips/mips-protos.h | 4 +-
gcc/config/mips/mips.cc | 14 ++-
gcc/config/rl78/rl78-protos.h | 4 +-
gcc/config/rl78/rl78.cc | 4 +-
gcc/config/rs6000/rs6000-string.cc | 10 +-
gcc/config/rs6000/rs6000.cc | 42 +++----
gcc/config/s390/s390.cc | 8 +-
gcc/emit-rtl.cc | 12 +-
gcc/genemit.cc | 57 +++++++--
gcc/genflags.cc | 65 +++++++++-
gcc/gensupport.cc | 13 +-
gcc/gensupport.h | 2 +-
gcc/rtl.cc | 97 +++++++++++----
gcc/rtl.h | 2 +
30 files changed, 413 insertions(+), 253 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-builtins.cc
b/gcc/config/aarch64/aarch64-builtins.cc
index 1d8baaef5c4..3df9d48c63f 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -3202,7 +3202,7 @@ aarch64_expand_builtin_rsqrt (int fcode, tree exp, rtx
target)
tree arg0 = CALL_EXPR_ARG (exp, 0);
rtx op0 = expand_normal (arg0);
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
switch (fcode)
{
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 1b4f56ce4ee..6a525b65e60 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -31716,7 +31716,7 @@ arm_block_set_unaligned_vect (rtx dstbase,
unsigned int i, nelt_v16, nelt_v8, nelt_mode;
rtx dst, mem;
rtx val_vec, reg;
- rtx (*gen_func) (rtx, rtx);
+ rtx_insn *(*gen_func) (rtx, rtx);
machine_mode mode;
unsigned HOST_WIDE_INT v = value;
unsigned int offset = 0;
diff --git a/gcc/config/avr/avr-passes.cc b/gcc/config/avr/avr-passes.cc
index d2b2d8421e0..403f57bf292 100644
--- a/gcc/config/avr/avr-passes.cc
+++ b/gcc/config/avr/avr-passes.cc
@@ -4132,8 +4132,9 @@ avr_optimize_casesi (rtx_insn *insns[5], rtx *xop)
rtx reg = copy_to_mode_reg (mode, xop[11]);
- rtx (*gen_add)(rtx,rtx,rtx) = QImode == mode ? gen_addqi3 : gen_addhi3;
- rtx (*gen_cbranch)(rtx,rtx,rtx,rtx)
+ rtx_insn *(*gen_add) (rtx, rtx, rtx)
+ = QImode == mode ? gen_insn_addqi3 : gen_addhi3;
+ rtx_insn *(*gen_cbranch)(rtx,rtx,rtx,rtx)
= QImode == mode ? gen_cbranchqi4 : gen_cbranchhi4;
emit_insn (gen_add (reg, reg, gen_int_mode (-low_idx, mode)));
diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h
index 8a971c0813e..b2774bee9b8 100644
--- a/gcc/config/avr/avr-protos.h
+++ b/gcc/config/avr/avr-protos.h
@@ -166,7 +166,8 @@ regmask (machine_mode mode, unsigned regno)
}
extern void avr_fix_inputs (rtx*, unsigned, unsigned);
-extern bool avr_emit3_fix_outputs (rtx (*)(rtx,rtx,rtx), rtx*, unsigned,
unsigned);
+extern bool avr_emit3_fix_outputs (rtx_insn *(*)(rtx, rtx, rtx),
+ rtx *, unsigned, unsigned);
extern rtx avr_add_ccclobber (rtx_insn *);
#define DONE_ADD_CCC emit (avr_add_ccclobber (curr_insn)); DONE;
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 2d0f9a8f31f..9108365e65f 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -15694,7 +15694,7 @@ avr_move_fixed_operands (rtx *op, rtx *hreg, unsigned
mask)
move the contents of respective pseudos to their hard regs. */
bool
-avr_emit3_fix_outputs (rtx (*gen)(rtx,rtx,rtx), rtx *op,
+avr_emit3_fix_outputs (rtx_insn *(*gen)(rtx,rtx,rtx), rtx *op,
unsigned opmask, unsigned rmask)
{
const int n = 3;
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 4980a04fdaf..7f8557145d8 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -806,7 +806,7 @@ static void
ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1)
{
rtx m;
- rtx (*extract) (rtx, rtx, rtx);
+ rtx_insn *(*extract) (rtx, rtx, rtx);
machine_mode mode;
if ((MEM_P (op1) && !TARGET_AVX256_SPLIT_UNALIGNED_LOAD)
@@ -5136,7 +5136,7 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code,
rtx cop0, rtx cop1,
|| !vector_all_ones_operand (optrue, data_mode)
|| opfalse != CONST0_RTX (data_mode))))
{
- rtx (*gen) (rtx, rtx, rtx) = NULL;
+ rtx_insn *(*gen) (rtx, rtx, rtx) = NULL;
switch (mode)
{
@@ -5176,21 +5176,21 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code,
rtx cop0, rtx cop1,
break;
case E_V8QImode:
if (code == GTU && TARGET_SSE2)
- gen = gen_uminv8qi3;
+ gen = gen_insn_uminv8qi3;
else if (code == GT && TARGET_SSE4_1)
- gen = gen_sminv8qi3;
+ gen = gen_insn_sminv8qi3;
break;
case E_V4QImode:
if (code == GTU && TARGET_SSE2)
- gen = gen_uminv4qi3;
+ gen = gen_insn_uminv4qi3;
else if (code == GT && TARGET_SSE4_1)
- gen = gen_sminv4qi3;
+ gen = gen_insn_sminv4qi3;
break;
case E_V2QImode:
if (code == GTU && TARGET_SSE2)
- gen = gen_uminv2qi3;
+ gen = gen_insn_uminv2qi3;
else if (code == GT && TARGET_SSE4_1)
- gen = gen_sminv2qi3;
+ gen = gen_insn_sminv2qi3;
break;
case E_V8HImode:
if (code == GTU && TARGET_SSE4_1)
@@ -5200,15 +5200,15 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code,
rtx cop0, rtx cop1,
break;
case E_V4HImode:
if (code == GTU && TARGET_SSE4_1)
- gen = gen_uminv4hi3;
+ gen = gen_insn_uminv4hi3;
else if (code == GT && TARGET_SSE2)
- gen = gen_sminv4hi3;
+ gen = gen_insn_sminv4hi3;
break;
case E_V2HImode:
if (code == GTU && TARGET_SSE4_1)
- gen = gen_uminv2hi3;
+ gen = gen_insn_uminv2hi3;
else if (code == GT && TARGET_SSE2)
- gen = gen_sminv2hi3;
+ gen = gen_insn_sminv2hi3;
break;
case E_V4SImode:
if (TARGET_SSE4_1)
@@ -5216,7 +5216,7 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code,
rtx cop0, rtx cop1,
break;
case E_V2SImode:
if (TARGET_SSE4_1)
- gen = (code == GTU) ? gen_uminv2si3 : gen_sminv2si3;
+ gen = (code == GTU) ? gen_insn_uminv2si3 : gen_insn_sminv2si3;
break;
case E_V2DImode:
if (TARGET_AVX512VL)
@@ -6709,7 +6709,7 @@ ix86_expand_ashl_const (rtx operand, int count,
machine_mode mode)
}
else
{
- rtx (*insn)(rtx, rtx, rtx);
+ rtx_insn *(*insn)(rtx, rtx, rtx);
insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3;
emit_insn (insn (operand, operand, GEN_INT (count)));
@@ -6719,7 +6719,7 @@ ix86_expand_ashl_const (rtx operand, int count,
machine_mode mode)
void
ix86_split_ashl (rtx *operands, rtx scratch, machine_mode mode)
{
- rtx (*gen_ashl3)(rtx, rtx, rtx);
+ rtx_insn *(*gen_ashl3)(rtx, rtx, rtx);
rtx (*gen_shld)(rtx, rtx, rtx);
int half_width = GET_MODE_BITSIZE (mode) >> 1;
machine_mode half_mode;
@@ -6800,9 +6800,9 @@ ix86_split_ashl (rtx *operands, rtx scratch, machine_mode
mode)
pentium4 a bit; no one else seems to care much either way. */
else
{
- rtx (*gen_lshr3)(rtx, rtx, rtx);
- rtx (*gen_and3)(rtx, rtx, rtx);
- rtx (*gen_xor3)(rtx, rtx, rtx);
+ rtx_insn *(*gen_lshr3)(rtx, rtx, rtx);
+ rtx_insn *(*gen_and3)(rtx, rtx, rtx);
+ rtx_insn *(*gen_xor3)(rtx, rtx, rtx);
HOST_WIDE_INT bits;
rtx x;
@@ -6874,7 +6874,7 @@ ix86_split_ashl (rtx *operands, rtx scratch, machine_mode
mode)
void
ix86_split_ashr (rtx *operands, rtx scratch, machine_mode mode)
{
- rtx (*gen_ashr3)(rtx, rtx, rtx)
+ rtx_insn *(*gen_ashr3)(rtx, rtx, rtx)
= mode == DImode ? gen_ashrsi3 : gen_ashrdi3;
rtx (*gen_shrd)(rtx, rtx, rtx);
int half_width = GET_MODE_BITSIZE (mode) >> 1;
@@ -6965,7 +6965,7 @@ ix86_split_ashr (rtx *operands, rtx scratch, machine_mode
mode)
void
ix86_split_lshr (rtx *operands, rtx scratch, machine_mode mode)
{
- rtx (*gen_lshr3)(rtx, rtx, rtx)
+ rtx_insn *(*gen_lshr3)(rtx, rtx, rtx)
= mode == DImode ? gen_lshrsi3 : gen_lshrdi3;
rtx (*gen_shrd)(rtx, rtx, rtx);
int half_width = GET_MODE_BITSIZE (mode) >> 1;
@@ -7110,7 +7110,7 @@ ix86_split_rshift_ndd (enum rtx_code code, rtx *operands,
rtx scratch)
gcc_assert (TARGET_APX_NDD);
int half_width = GET_MODE_BITSIZE (TImode) >> 1;
bool ashr_p = code == ASHIFTRT;
- rtx (*gen_shr)(rtx, rtx, rtx) = ashr_p ? gen_ashrdi3
+ rtx_insn *(*gen_shr)(rtx, rtx, rtx) = ashr_p ? gen_ashrdi3
: gen_lshrdi3;
rtx low[2], high[2];
@@ -7221,7 +7221,7 @@ ix86_expand_v1ti_shift (enum rtx_code code, rtx
operands[])
{
rtx tmp1 = ix86_expand_v1ti_to_ti (op1);
rtx tmp2 = gen_reg_rtx (TImode);
- rtx (*shift) (rtx, rtx, rtx)
+ rtx_insn *(*shift) (rtx, rtx, rtx)
= (code == ASHIFT) ? gen_ashlti3 : gen_lshrti3;
emit_insn (shift (tmp2, tmp1, operands[2]));
rtx tmp3 = ix86_expand_ti_to_v1ti (tmp2);
@@ -7302,7 +7302,7 @@ ix86_expand_v1ti_rotate (enum rtx_code code, rtx
operands[])
{
rtx tmp1 = ix86_expand_v1ti_to_ti (op1);
rtx tmp2 = gen_reg_rtx (TImode);
- rtx (*rotate) (rtx, rtx, rtx)
+ rtx_insn *(*rotate) (rtx, rtx, rtx)
= (code == ROTATE) ? gen_rotlti3 : gen_rotrti3;
emit_insn (rotate (tmp2, tmp1, operands[2]));
rtx tmp3 = ix86_expand_ti_to_v1ti (tmp2);
@@ -18979,14 +18979,14 @@ ix86_expand_vector_init_interleave (machine_mode mode,
machine_mode first_imode, second_imode, third_imode, inner_mode;
int i, j;
rtx op, op0, op1;
- rtx (*gen_load_even) (rtx, rtx, rtx);
+ rtx_insn *(*gen_load_even) (rtx, rtx, rtx);
rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
switch (mode)
{
case E_V8HFmode:
- gen_load_even = gen_vec_interleave_lowv8hf;
+ gen_load_even = gen_insn_vec_interleave_lowv8hf;
gen_interleave_first_low = gen_vec_interleave_lowv4si;
gen_interleave_second_low = gen_vec_interleave_lowv2di;
inner_mode = HFmode;
@@ -18995,7 +18995,7 @@ ix86_expand_vector_init_interleave (machine_mode mode,
third_imode = VOIDmode;
break;
case E_V8BFmode:
- gen_load_even = gen_vec_interleave_lowv8bf;
+ gen_load_even = gen_insn_vec_interleave_lowv8bf;
gen_interleave_first_low = gen_vec_interleave_lowv4si;
gen_interleave_second_low = gen_vec_interleave_lowv2di;
inner_mode = BFmode;
@@ -21215,7 +21215,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx
val, int elt)
};
int i, j, n;
machine_mode mmode = VOIDmode;
- rtx (*gen_blendm) (rtx, rtx, rtx, rtx);
+ rtx_insn *(*gen_blendm) (rtx, rtx, rtx, rtx);
if (!IN_RANGE (elt, 0, GET_MODE_NUNITS (mode)))
{
@@ -21500,7 +21500,7 @@ half:
if (TARGET_AVX512F)
{
mmode = QImode;
- gen_blendm = gen_avx512f_blendmv8df;
+ gen_blendm = gen_insn_avx512f_blendmv8df;
}
break;
@@ -21508,7 +21508,7 @@ half:
if (TARGET_AVX512F)
{
mmode = QImode;
- gen_blendm = gen_avx512f_blendmv8di;
+ gen_blendm = gen_insn_avx512f_blendmv8di;
}
break;
@@ -21516,7 +21516,7 @@ half:
if (TARGET_AVX512F)
{
mmode = HImode;
- gen_blendm = gen_avx512f_blendmv16sf;
+ gen_blendm = gen_insn_avx512f_blendmv16sf;
}
break;
@@ -21524,7 +21524,7 @@ half:
if (TARGET_AVX512F)
{
mmode = HImode;
- gen_blendm = gen_avx512f_blendmv16si;
+ gen_blendm = gen_insn_avx512f_blendmv16si;
}
break;
@@ -21532,21 +21532,21 @@ half:
if (TARGET_AVX512BW)
{
mmode = SImode;
- gen_blendm = gen_avx512bw_blendmv32hf;
+ gen_blendm = gen_insn_avx512bw_blendmv32hf;
}
break;
case E_V32BFmode:
if (TARGET_AVX512BW)
{
mmode = SImode;
- gen_blendm = gen_avx512bw_blendmv32bf;
+ gen_blendm = gen_insn_avx512bw_blendmv32bf;
}
break;
case E_V32HImode:
if (TARGET_AVX512BW)
{
mmode = SImode;
- gen_blendm = gen_avx512bw_blendmv32hi;
+ gen_blendm = gen_insn_avx512bw_blendmv32hi;
}
else if (TARGET_AVX512F)
{
@@ -21560,7 +21560,7 @@ half:
if (TARGET_AVX512BW)
{
mmode = DImode;
- gen_blendm = gen_avx512bw_blendmv64qi;
+ gen_blendm = gen_insn_avx512bw_blendmv64qi;
}
else if (TARGET_AVX512F)
{
@@ -22153,7 +22153,7 @@ emit_reduc_half (rtx dest, rtx src, int i)
DEST is the destination; IN is the input vector. */
void
-ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
+ix86_expand_reduc (rtx_insn *(*fn) (rtx, rtx, rtx), rtx dest, rtx in)
{
rtx half, dst, vec = in;
machine_mode mode = GET_MODE (in);
@@ -22539,7 +22539,7 @@ ix86_emit_i387_round (rtx op0, rtx op1)
rtx res = gen_reg_rtx (outmode);
rtx_code_label *jump_label = gen_label_rtx ();
rtx (*floor_insn) (rtx, rtx);
- rtx (*neg_insn) (rtx, rtx);
+ rtx_insn *(*neg_insn) (rtx, rtx);
rtx_insn *insn;
rtx tmp;
@@ -23520,7 +23520,7 @@ ix86_expand_round_sse4 (rtx op0, rtx op1)
rtx e1, e2, res, half;
const struct real_format *fmt;
REAL_VALUE_TYPE pred_half, half_minus_pred_half;
- rtx (*gen_copysign) (rtx, rtx, rtx);
+ rtx_insn *(*gen_copysign) (rtx, rtx, rtx);
rtx (*gen_round) (rtx, rtx, rtx);
switch (mode)
@@ -25759,7 +25759,7 @@ static bool
expand_vec_perm_interleave3 (struct expand_vec_perm_d *d)
{
unsigned i, nelt;
- rtx (*gen) (rtx, rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx, rtx);
if (d->one_operand_p)
return false;
@@ -26141,7 +26141,7 @@ expand_vec_perm_psrlw_psllw_por (struct
expand_vec_perm_d *d)
unsigned i;
rtx (*gen_shr) (rtx, rtx, rtx);
rtx (*gen_shl) (rtx, rtx, rtx);
- rtx (*gen_or) (rtx, rtx, rtx);
+ rtx_insn *(*gen_or) (rtx, rtx, rtx);
machine_mode mode = VOIDmode;
if (!TARGET_SSE2 || !d->one_operand_p)
@@ -26155,7 +26155,7 @@ expand_vec_perm_psrlw_psllw_por (struct
expand_vec_perm_d *d)
mode = V4HImode;
gen_shr = gen_lshrv4hi3;
gen_shl = gen_ashlv4hi3;
- gen_or = gen_iorv4hi3;
+ gen_or = gen_insn_iorv4hi3;
break;
case E_V16QImode:
mode = V8HImode;
@@ -26637,8 +26637,8 @@ expand_vec_perm_pslldq_psrldq_por (struct
expand_vec_perm_d *d, bool pandn)
bool clear_op0, clear_op1;
unsigned inner_size;
rtx op0, op1, dop1;
- rtx (*gen_vec_shr) (rtx, rtx, rtx);
- rtx (*gen_vec_shl) (rtx, rtx, rtx);
+ rtx_insn *(*gen_vec_shr) (rtx, rtx, rtx);
+ rtx_insn *(*gen_vec_shl) (rtx, rtx, rtx);
/* pshufd can be used for V4SI/V2DI under TARGET_SSE2. */
if (!TARGET_SSE2 || (vmode != E_V16QImode && vmode != E_V8HImode))
@@ -26733,7 +26733,7 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d
*d)
int pblendw_i = 0;
bool end_perm = false;
machine_mode half_mode;
- rtx (*gen_and) (rtx, rtx, rtx);
+ rtx_insn *(*gen_and) (rtx, rtx, rtx);
rtx (*gen_pack) (rtx, rtx, rtx);
rtx (*gen_shift) (rtx, rtx, rtx);
@@ -26749,7 +26749,7 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d
*d)
c = 0xffff;
s = 16;
half_mode = V2SImode;
- gen_and = gen_andv2si3;
+ gen_and = gen_insn_andv2si3;
gen_pack = gen_mmx_packusdw;
gen_shift = gen_lshrv2si3;
pblendw_i = 0x5;
@@ -26771,7 +26771,7 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d
*d)
c = 0xff;
s = 8;
half_mode = V4HImode;
- gen_and = gen_andv4hi3;
+ gen_and = gen_insn_andv4hi3;
gen_pack = gen_mmx_packuswb;
gen_shift = gen_lshrv4hi3;
break;
@@ -28069,9 +28069,9 @@ ix86_expand_vec_shift_qihi_constant (enum rtx_code code,
rtx vec_const_and, vec_const_xor;
rtx tmp, op1_subreg;
rtx (*gen_shift) (rtx, rtx, rtx);
- rtx (*gen_and) (rtx, rtx, rtx);
- rtx (*gen_xor) (rtx, rtx, rtx);
- rtx (*gen_sub) (rtx, rtx, rtx);
+ rtx_insn *(*gen_and) (rtx, rtx, rtx);
+ rtx_insn *(*gen_xor) (rtx, rtx, rtx);
+ rtx_insn *(*gen_sub) (rtx, rtx, rtx);
/* Only optimize shift by constant. */
if (!CONST_INT_P (op2))
@@ -28327,7 +28327,7 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest,
rtx op1, rtx op2)
machine_mode himode, qimode = GET_MODE (dest);
machine_mode wqimode;
rtx qop1, qop2, hop1, hop2, hdest;
- rtx (*gen_truncate)(rtx, rtx) = NULL;
+ rtx_insn *(*gen_truncate) (rtx, rtx) = NULL;
bool op2vec = GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT;
bool uns_p = code != ASHIFTRT;
@@ -28355,7 +28355,7 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest,
rtx op1, rtx op2)
break;
case E_V32QImode:
himode = V32HImode;
- gen_truncate = gen_truncv32hiv32qi2;
+ gen_truncate = gen_insn_truncv32hiv32qi2;
break;
default:
gcc_unreachable ();
@@ -28405,8 +28405,8 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest,
rtx op1, rtx op2)
{
machine_mode qimode = GET_MODE (dest);
machine_mode himode;
- rtx (*gen_il) (rtx, rtx, rtx);
- rtx (*gen_ih) (rtx, rtx, rtx);
+ rtx_insn *(*gen_il) (rtx, rtx, rtx);
+ rtx_insn *(*gen_ih) (rtx, rtx, rtx);
rtx op1_l, op1_h, op2_l, op2_h, res_l, res_h;
bool op2vec = GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT;
struct expand_vec_perm_d d;
@@ -28449,17 +28449,17 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest,
rtx op1, rtx op2)
switch (qimode)
{
case E_V16QImode:
- gen_il = gen_vec_interleave_lowv16qi;
- gen_ih = gen_vec_interleave_highv16qi;
+ gen_il = gen_insn_vec_interleave_lowv16qi;
+ gen_ih = gen_insn_vec_interleave_highv16qi;
break;
case E_V32QImode:
- gen_il = gen_avx2_interleave_lowv32qi;
- gen_ih = gen_avx2_interleave_highv32qi;
+ gen_il = gen_insn_avx2_interleave_lowv32qi;
+ gen_ih = gen_insn_avx2_interleave_highv32qi;
full_interleave = false;
break;
case E_V64QImode:
- gen_il = gen_avx512bw_interleave_lowv64qi;
- gen_ih = gen_avx512bw_interleave_highv64qi;
+ gen_il = gen_insn_avx512bw_interleave_lowv64qi;
+ gen_ih = gen_insn_avx512bw_interleave_highv64qi;
full_interleave = false;
break;
default:
@@ -28848,7 +28848,7 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2)
else
{
machine_mode nmode;
- rtx (*umul) (rtx, rtx, rtx);
+ rtx_insn *(*umul) (rtx, rtx, rtx);
if (mode == V2DImode)
{
@@ -28901,7 +28901,7 @@ ix86_expand_umulvndi_highpart (rtx op0, rtx op1, rtx
op2)
{
/* The following sequence can be used with SSE2. */
machine_mode mode = GET_MODE (op0);
- rtx (*umul) (rtx, rtx, rtx);
+ rtx_insn *(*umul) (rtx, rtx, rtx);
machine_mode nmode;
if (mode == V2DImode)
{
@@ -29213,7 +29213,7 @@ ix86_expand_pinsr (rtx *operands)
case E_V1TImode:
{
machine_mode srcmode, dstmode;
- rtx (*pinsr)(rtx, rtx, rtx, rtx);
+ rtx_insn *(*pinsr)(rtx, rtx, rtx, rtx);
rtx d;
if (!int_mode_for_size (size, 0).exists (&srcmode))
@@ -29225,21 +29225,21 @@ ix86_expand_pinsr (rtx *operands)
if (!TARGET_SSE4_1)
return false;
dstmode = V16QImode;
- pinsr = gen_sse4_1_pinsrb;
+ pinsr = gen_insn_sse4_1_pinsrb;
break;
case E_HImode:
if (!TARGET_SSE2)
return false;
dstmode = V8HImode;
- pinsr = gen_sse2_pinsrw;
+ pinsr = gen_insn_sse2_pinsrw;
break;
case E_SImode:
if (!TARGET_SSE4_1)
return false;
dstmode = V4SImode;
- pinsr = gen_sse4_1_pinsrd;
+ pinsr = gen_insn_sse4_1_pinsrd;
break;
case E_DImode:
@@ -29247,7 +29247,7 @@ ix86_expand_pinsr (rtx *operands)
if (!TARGET_SSE4_1)
return false;
dstmode = V2DImode;
- pinsr = gen_sse4_1_pinsrq;
+ pinsr = gen_insn_sse4_1_pinsrq;
break;
default:
@@ -29403,8 +29403,8 @@ ix86_expand_cmpxchg_loop (rtx *ptarget_bool, rtx
target_val,
rtx_code_label *cmp_label = NULL;
rtx_code_label *done_label = NULL;
rtx target_bool = NULL_RTX, new_mem = NULL_RTX;
- rtx (*gen) (rtx, rtx, rtx, rtx, rtx) = NULL;
- rtx (*gendw) (rtx, rtx, rtx, rtx, rtx, rtx) = NULL;
+ rtx_insn *(*gen) (rtx, rtx, rtx, rtx, rtx) = NULL;
+ rtx_insn *(*gendw) (rtx, rtx, rtx, rtx, rtx, rtx) = NULL;
machine_mode mode = GET_MODE (target_val), hmode = mode;
if (*ptarget_bool == NULL)
@@ -29422,26 +29422,26 @@ ix86_expand_cmpxchg_loop (rtx *ptarget_bool, rtx
target_val,
switch (mode)
{
case E_TImode:
- gendw = gen_atomic_compare_and_swapti_doubleword;
+ gendw = gen_insn_atomic_compare_and_swapti_doubleword;
hmode = DImode;
break;
case E_DImode:
if (doubleword)
{
- gendw = gen_atomic_compare_and_swapdi_doubleword;
+ gendw = gen_insn_atomic_compare_and_swapdi_doubleword;
hmode = SImode;
}
else
- gen = gen_atomic_compare_and_swapdi_1;
+ gen = gen_insn_atomic_compare_and_swapdi_1;
break;
case E_SImode:
- gen = gen_atomic_compare_and_swapsi_1;
+ gen = gen_insn_atomic_compare_and_swapsi_1;
break;
case E_HImode:
- gen = gen_atomic_compare_and_swaphi_1;
+ gen = gen_insn_atomic_compare_and_swaphi_1;
break;
case E_QImode:
- gen = gen_atomic_compare_and_swapqi_1;
+ gen = gen_insn_atomic_compare_and_swapqi_1;
break;
default:
gcc_unreachable ();
@@ -30666,7 +30666,7 @@ ix86_expand_bitreverse (rtx dest, rtx src)
}
rtx temp4 = gen_reg_rtx (GET_MODE (target));
rtx temp5 = gen_reg_rtx (GET_MODE (target));
- rtx (*gen_bswap) (rtx, rtx)
+ rtx_insn *(*gen_bswap) (rtx, rtx)
= mode == TImode ? gen_bswapdi2 : gen_bswapsi2;
emit_insn (gen_bswap (temp4, target));
emit_insn (gen_bswap (temp5, temp1));
diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index 8ac329a716a..377514eb585 100644
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -303,7 +303,7 @@ extern void ix86_expand_vector_init (bool, rtx, rtx);
extern void ix86_expand_vector_set (bool, rtx, rtx, int);
extern void ix86_expand_vector_set_var (rtx, rtx, rtx);
extern void ix86_expand_vector_extract (bool, rtx, rtx, int);
-extern void ix86_expand_reduc (rtx (*)(rtx, rtx, rtx), rtx, rtx);
+extern void ix86_expand_reduc (rtx_insn *(*)(rtx, rtx, rtx), rtx, rtx);
extern void ix86_expand_vec_extract_even_odd (rtx, rtx, rtx, unsigned);
extern bool ix86_expand_pextr (rtx *);
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2d2e620713f..ab3cb9134aa 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -19124,7 +19124,7 @@
operands[4] = gen_reg_rtx (QImode);
- rtx (*insn)(rtx, rtx) = (cnt == 0) ? gen_negqi2 : gen_one_cmplqi2;
+ rtx_insn *(*insn)(rtx, rtx) = (cnt == 0) ? gen_negqi2 : gen_one_cmplqi2;
emit_insn (insn (operands[4], operands[2]));
}
[(set_attr "isa" "*,bmi2")])
@@ -19154,7 +19154,7 @@
operands[4] = gen_reg_rtx (QImode);
- rtx (*insn)(rtx, rtx) = (cnt == 0) ? gen_negqi2 : gen_one_cmplqi2;
+ rtx_insn *(*insn)(rtx, rtx) = (cnt == 0) ? gen_negqi2 : gen_one_cmplqi2;
emit_insn (insn (operands[4], operands[2]));
}
[(set_attr "isa" "*,bmi2")])
@@ -19265,8 +19265,8 @@
rtx tmp_hi = gen_reg_rtx (DImode);
emit_move_insn (tmp_lo, src_lo);
emit_move_insn (tmp_hi, src_hi);
- rtx (*shiftd) (rtx, rtx, rtx)
- = (<CODE> == ROTATE) ? gen_x86_64_shld : gen_x86_64_shrd;
+ rtx_insn *(*shiftd) (rtx, rtx, rtx)
+ = (<CODE> == ROTATE) ? gen_insn_x86_64_shld : gen_insn_x86_64_shrd;
emit_insn (shiftd (tmp_lo, src_hi, amount));
emit_insn (shiftd (tmp_hi, src_lo, amount));
rtx dst_lo = gen_lowpart (DImode, operands[0]);
@@ -25291,7 +25291,7 @@
(use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
- rtx (*gen_truncxf) (rtx, rtx);
+ rtx_insn *(*gen_truncxf) (rtx, rtx);
rtx_code_label *label = gen_label_rtx ();
@@ -25310,9 +25310,9 @@
/* Truncate the result properly for strict SSE math. */
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !TARGET_MIX_SSE_I387)
- gen_truncxf = gen_truncxf<mode>2;
+ gen_truncxf = gen_insn_truncxf<mode>2;
else
- gen_truncxf = gen_truncxf<mode>2_i387_noop_unspec;
+ gen_truncxf = gen_insn_truncxf<mode>2_i387_noop_unspec;
emit_insn (gen_truncxf (operands[0], op1));
DONE;
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 96e173efaa5..7dce82eecfd 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3050,7 +3050,7 @@
rtx op1 = gen_reg_rtx (V8HImode);
rtx op0 = gen_reg_rtx (V8HFmode);
- rtx (*gen_movd_sse) (rtx, rtx)
+ rtx_insn *(*gen_movd_sse) (rtx, rtx)
= gen_mov<mov_to_sse_suffix>_<mmxintvecmodelower>_to_sse;
emit_insn (gen_movd_sse (op1, operands[1]));
@@ -6570,7 +6570,7 @@
"TARGET_MMX_WITH_SSE"
{
rtx tmp = gen_reg_rtx (<MODE>mode);
- ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
+ ix86_expand_reduc (gen_insn_<code><mode>3, tmp, operands[1]);
emit_insn (gen_vec_extract<mode><mmxscalarmodelower> (operands[0],
tmp, const0_rtx));
DONE;
@@ -6610,7 +6610,7 @@
"TARGET_MMX_WITH_SSE"
{
rtx tmp = gen_reg_rtx (V4HImode);
- ix86_expand_reduc (gen_addv4hi3, tmp, operands[1]);
+ ix86_expand_reduc (gen_insn_addv4hi3, tmp, operands[1]);
emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
DONE;
})
@@ -6622,7 +6622,7 @@
"TARGET_MMX_WITH_SSE"
{
rtx tmp = gen_reg_rtx (V4HImode);
- ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
+ ix86_expand_reduc (gen_insn_<code>v4hi3, tmp, operands[1]);
emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
DONE;
})
@@ -6634,7 +6634,7 @@
"TARGET_SSE4_1"
{
rtx tmp = gen_reg_rtx (V4QImode);
- ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
+ ix86_expand_reduc (gen_insn_<code>v4qi3, tmp, operands[1]);
emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
DONE;
})
@@ -6646,7 +6646,7 @@
"TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
{
rtx tmp = gen_reg_rtx (V4HImode);
- ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
+ ix86_expand_reduc (gen_insn_<code>v4hi3, tmp, operands[1]);
emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
DONE;
})
@@ -6658,7 +6658,7 @@
"TARGET_SSE4_1"
{
rtx tmp = gen_reg_rtx (V4QImode);
- ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
+ ix86_expand_reduc (gen_insn_<code>v4qi3, tmp, operands[1]);
emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
DONE;
})
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3a445c9746d..853ecddb359 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7965,7 +7965,7 @@
""
{
rtx tem;
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode != V8HFmode)
{
tem = gen_reg_rtx (<ssehalfvecmode>mode);
@@ -7977,7 +7977,7 @@
{
tem = force_reg (V8HFmode, operands[1]);
tem = lowpart_subreg (V4HFmode, tem, V8HFmode);
- gen = gen_extendv4hfv4sf2;
+ gen = gen_insn_extendv4hfv4sf2;
}
emit_insn (gen (operands[0], tem));
@@ -7990,7 +7990,7 @@
""
{
rtx tem;
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode != V8HFmode)
{
tem = gen_reg_rtx (<ssehalfvecmode>mode);
@@ -8009,7 +8009,7 @@
emit_move_insn (tem,
gen_rtx_VEC_SELECT (V8HFmode, operands[1], selector));
tem = lowpart_subreg (V4HFmode, tem, V8HFmode);
- gen = gen_extendv4hfv4sf2;
+ gen = gen_insn_extendv4hfv4sf2;
}
emit_insn (gen (operands[0], tem));
@@ -10002,12 +10002,12 @@
{
rtx r1 = gen_reg_rtx (<vpckfloat_temp_mode>mode);
rtx r2 = gen_reg_rtx (<vpckfloat_temp_mode>mode);
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode == V2DImode)
gen = gen_avx512dq_float<floatunssuffix>v2div2sf2;
else
- gen = gen_float<floatunssuffix><mode><vpckfloat_op_mode>2;
+ gen = gen_insn_float<floatunssuffix><mode><vpckfloat_op_mode>2;
emit_insn (gen (r1, operands[1]));
emit_insn (gen (r2, operands[2]));
if (<MODE>mode == V2DImode)
@@ -10027,12 +10027,12 @@
{
rtx r1 = gen_reg_rtx (<vpckfloat_temp_mode>mode);
rtx r2 = gen_reg_rtx (<vpckfloat_temp_mode>mode);
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode == V4SImode)
gen = gen_avx512fp16_float<floatunssuffix>v4siv4hf2;
else
- gen = gen_float<floatunssuffix><mode><vpckfloat_op_mode>2;
+ gen = gen_insn_float<floatunssuffix><mode><vpckfloat_op_mode>2;
emit_insn (gen (r1, operands[1]));
emit_insn (gen (r2, operands[2]));
if (<MODE>mode == V4SImode)
@@ -10559,17 +10559,17 @@
"TARGET_AVX512DQ"
{
rtx tem = operands[1];
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode != V4SFmode)
{
tem = gen_reg_rtx (<ssehalfvecmode>mode);
emit_insn (gen_vec_extract_lo_<vunpckfixt_extract_mode> (tem,
operands[1]));
- gen =
gen_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
+gen = gen_insn_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
}
else
- gen = gen_avx512dq_fix<fixunssuffix>_truncv2sfv2di2;
+ gen = gen_insn_avx512dq_fix<fixunssuffix>_truncv2sfv2di2;
emit_insn (gen (operands[0], tem));
DONE;
@@ -10582,20 +10582,20 @@
"TARGET_AVX512DQ"
{
rtx tem;
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode != V4SFmode)
{
tem = gen_reg_rtx (<ssehalfvecmode>mode);
emit_insn (gen_vec_extract_hi_<vunpckfixt_extract_mode> (tem,
operands[1]));
- gen =
gen_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
+gen = gen_insn_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
}
else
{
tem = gen_reg_rtx (V4SFmode);
emit_insn (gen_avx_vpermilv4sf (tem, operands[1], GEN_INT (0x4e)));
- gen = gen_avx512dq_fix<fixunssuffix>_truncv2sfv2di2;
+ gen = gen_insn_avx512dq_fix<fixunssuffix>_truncv2sfv2di2;
}
emit_insn (gen (operands[0], tem));
@@ -10609,16 +10609,16 @@
"TARGET_AVX512FP16"
{
rtx tem = operands[1];
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode != V8HFmode)
{
tem = gen_reg_rtx (<ssehalfvecmode>mode);
emit_insn (gen_vec_extract_lo_<vunpckfixt_extract_mode> (tem,
operands[1]));
- gen =
gen_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
+gen = gen_insn_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
}
else
- gen = gen_avx512fp16_fix<fixunssuffix>_trunc<vunpckfixt_model>2;
+ gen = gen_insn_avx512fp16_fix<fixunssuffix>_trunc<vunpckfixt_model>2;
emit_insn (gen (operands[0], tem));
DONE;
@@ -10631,13 +10631,13 @@
"TARGET_AVX512FP16"
{
rtx tem = operands[1];
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode != V8HFmode)
{
tem = gen_reg_rtx (<ssehalfvecmode>mode);
emit_insn (gen_vec_extract_hi_<vunpckfixt_extract_mode> (tem,
operands[1]));
- gen =
gen_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
+gen = gen_insn_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
}
else
{
@@ -10649,7 +10649,7 @@
rtx selector = gen_rtx_PARALLEL (VOIDmode, tmp);
emit_move_insn (tem,
gen_rtx_VEC_SELECT (V8HFmode, operands[1], selector));
- gen = gen_avx512fp16_fix<fixunssuffix>_trunc<vunpckfixt_model>2;
+ gen = gen_insn_avx512fp16_fix<fixunssuffix>_trunc<vunpckfixt_model>2;
}
emit_insn (gen (operands[0], tem));
@@ -11550,7 +11550,7 @@
{
rtx r1 = gen_reg_rtx (<vpckfloat_temp_mode>mode);
rtx r2 = gen_reg_rtx (<vpckfloat_temp_mode>mode);
- rtx (*gen) (rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx);
if (<MODE>mode == V4SFmode)
gen = gen_f16c_truncv4sfv8hf2;
@@ -13533,7 +13533,7 @@
(match_operand:QI 4 "register_operand")]
"TARGET_AVX512F"
{
- rtx (*insn)(rtx, rtx, rtx, rtx);
+ rtx_insn *(*insn)(rtx, rtx, rtx, rtx);
rtx dest = operands[0];
if (MEM_P (dest) && !rtx_equal_p (dest, operands[3]))
@@ -13542,10 +13542,10 @@
switch (INTVAL (operands[2]))
{
case 0:
- insn = gen_vec_extract_lo_<mode>_mask;
+ insn = gen_insn_vec_extract_lo_<mode>_mask;
break;
case 1:
- insn = gen_vec_extract_hi_<mode>_mask;
+ insn = gen_insn_vec_extract_hi_<mode>_mask;
break;
default:
gcc_unreachable ();
@@ -13685,7 +13685,7 @@
(match_operand:QI 4 "register_operand")]
"TARGET_AVX512VL"
{
- rtx (*insn)(rtx, rtx, rtx, rtx);
+ rtx_insn *(*insn)(rtx, rtx, rtx, rtx);
rtx dest = operands[0];
if (MEM_P (dest)
@@ -13702,10 +13702,10 @@
switch (INTVAL (operands[2]))
{
case 0:
- insn = gen_vec_extract_lo_<mode>_mask;
+ insn = gen_insn_vec_extract_lo_<mode>_mask;
break;
case 1:
- insn = gen_vec_extract_hi_<mode>_mask;
+ insn = gen_insn_vec_extract_hi_<mode>_mask;
break;
default:
gcc_unreachable ();
@@ -13723,15 +13723,15 @@
(match_operand:SI 2 "const_0_to_1_operand")]
"TARGET_AVX"
{
- rtx (*insn)(rtx, rtx);
+ rtx_insn *(*insn)(rtx, rtx);
switch (INTVAL (operands[2]))
{
case 0:
- insn = gen_vec_extract_lo_<mode>;
+ insn = gen_insn_vec_extract_lo_<mode>;
break;
case 1:
- insn = gen_vec_extract_hi_<mode>;
+ insn = gen_insn_vec_extract_hi_<mode>;
break;
default:
gcc_unreachable ();
@@ -28141,7 +28141,7 @@
if (TARGET_XOP && <MODE>mode == V16QImode)
{
bool negate = false;
- rtx (*gen) (rtx, rtx, rtx);
+ rtx_insn *(*gen) (rtx, rtx, rtx);
rtx tmp, par;
int i;
@@ -28163,7 +28163,9 @@
if (negate)
emit_insn (gen_negv16qi2 (tmp, tmp));
- gen = (<CODE> == LSHIFTRT ? gen_xop_shlv16qi3 : gen_xop_shav16qi3);
+ gen = ((<CODE> == LSHIFTRT)
+ ? gen_insn_xop_shlv16qi3
+ : gen_insn_xop_shav16qi3);
emit_insn (gen (operands[0], operands[1], tmp));
}
else if (TARGET_GFNI && CONST_INT_P (operands[2])
@@ -29732,15 +29734,15 @@
(match_operand:<avx512fmaskmode> 5 "register_operand")]
"TARGET_AVX512VL"
{
- rtx (*insn)(rtx, rtx, rtx, rtx, rtx);
+ rtx_insn *(*insn)(rtx, rtx, rtx, rtx, rtx);
switch (INTVAL (operands[3]))
{
case 0:
- insn = gen_vec_set_lo_<mode>_mask;
+ insn = gen_insn_vec_set_lo_<mode>_mask;
break;
case 1:
- insn = gen_vec_set_hi_<mode>_mask;
+ insn = gen_insn_vec_set_hi_<mode>_mask;
break;
default:
gcc_unreachable ();
@@ -29758,15 +29760,15 @@
(match_operand:SI 3 "const_0_to_1_operand")]
"TARGET_AVX"
{
- rtx (*insn)(rtx, rtx, rtx);
+ rtx_insn *(*insn)(rtx, rtx, rtx);
switch (INTVAL (operands[3]))
{
case 0:
- insn = gen_vec_set_lo_<mode>;
+ insn = gen_insn_vec_set_lo_<mode>;
break;
case 1:
- insn = gen_vec_set_hi_<mode>;
+ insn = gen_insn_vec_set_hi_<mode>;
break;
default:
gcc_unreachable ();
diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 19bf1757aee..dce2a308f64 100644
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -125,15 +125,15 @@
enough not to require barriers of any kind. */
if (is_mm_seq_cst (model))
{
- rtx (*mfence_insn)(rtx);
+ rtx_insn *(*mfence_insn)(rtx);
rtx mem;
if ((TARGET_64BIT || TARGET_SSE2)
&& (optimize_function_for_size_p (cfun)
|| !TARGET_AVOID_MFENCE))
- mfence_insn = gen_mfence_sse2;
+ mfence_insn = gen_insn_mfence_sse2;
else
- mfence_insn = gen_mfence_nosse;
+ mfence_insn = gen_insn_mfence_nosse;
mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (mem) = 1;
diff --git a/gcc/config/ia64/ia64.cc b/gcc/config/ia64/ia64.cc
index 221388c43c8..cba2b4ec6cd 100644
--- a/gcc/config/ia64/ia64.cc
+++ b/gcc/config/ia64/ia64.cc
@@ -189,11 +189,11 @@ static void ia64_compute_frame_size (HOST_WIDE_INT);
static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
static void finish_spill_pointers (void);
static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
-static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
-static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
-static rtx gen_movdi_x (rtx, rtx, rtx);
-static rtx gen_fr_spill_x (rtx, rtx, rtx);
-static rtx gen_fr_restore_x (rtx, rtx, rtx);
+static void do_spill (rtx_insn *(*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
+static void do_restore (rtx_insn *(*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
+static rtx_insn *gen_movdi_x (rtx, rtx, rtx);
+static rtx_insn *gen_fr_spill_x (rtx, rtx, rtx);
+static rtx_insn *gen_fr_restore_x (rtx, rtx, rtx);
static void ia64_option_override (void);
static bool ia64_can_eliminate (const int, const int);
@@ -3208,7 +3208,7 @@ spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
}
static void
-do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
+do_spill (rtx_insn *(*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
rtx frame_reg)
{
int iter = spill_fill_data.next_iter;
@@ -3250,7 +3250,8 @@ do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg,
HOST_WIDE_INT cfa_off,
}
static void
-do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
+do_restore (rtx_insn *(*move_fn) (rtx, rtx, rtx), rtx reg,
+ HOST_WIDE_INT cfa_off)
{
int iter = spill_fill_data.next_iter;
rtx_insn *insn;
@@ -3264,22 +3265,22 @@ do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg,
HOST_WIDE_INT cfa_off)
exist so that we can give gr_spill/gr_fill the offset they need and
use a consistent function interface. */
-static rtx
+static rtx_insn *
gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
{
- return gen_movdi (dest, src);
+ return gen_insn_movdi (dest, src);
}
-static rtx
+static rtx_insn *
gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
{
- return gen_fr_spill (dest, src);
+ return gen_insn_fr_spill (dest, src);
}
-static rtx
+static rtx_insn *
gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
{
- return gen_fr_restore (dest, src);
+ return gen_insn_fr_restore (dest, src);
}
#define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 23ba70c97dc..d0cdb8d4378 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -3570,9 +3570,9 @@
(const_int zero_one)]
"ISA_HAS_LASX"
{
- rtx (*fn_even) (rtx, rtx, rtx) =
+rtx_insn *(*fn_even) (rtx, rtx, rtx) =
gen_lasx_xv<optab>wev_<dlasxfmt>_<lasxfmt><u>;
- rtx (*fn_odd) (rtx, rtx, rtx) =
+rtx_insn *(*fn_odd) (rtx, rtx, rtx) =
gen_lasx_xv<optab>wod_<dlasxfmt>_<lasxfmt><u>;
loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
<zero_one>, fn_even, fn_odd);
@@ -3587,9 +3587,9 @@ gen_lasx_xv<optab>wod_<dlasxfmt>_<lasxfmt><u>;
(const_int zero_one)]
"ISA_HAS_LASX"
{
- rtx (*fn_even) (rtx, rtx, rtx) =
+rtx_insn *(*fn_even) (rtx, rtx, rtx) =
gen_lasx_xvmulwev_<dlasxfmt>_<lasxfmt><u>;
- rtx (*fn_odd) (rtx, rtx, rtx) =
+rtx_insn *(*fn_odd) (rtx, rtx, rtx) =
gen_lasx_xvmulwod_<dlasxfmt>_<lasxfmt><u>;
loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
<zero_one>, fn_even, fn_odd);
diff --git a/gcc/config/loongarch/loongarch-protos.h
b/gcc/config/loongarch/loongarch-protos.h
index 0289409226f..eb0ac098f11 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -201,7 +201,7 @@ extern void loongarch_expand_vec_cond_expr (machine_mode,
machine_mode, rtx *);
extern void loongarch_expand_vec_cond_mask_expr (machine_mode, machine_mode,
rtx *);
extern void loongarch_expand_vec_widen_hilo (rtx, rtx, rtx, bool,
- rtx (*)(rtx, rtx, rtx), rtx (*)(rtx, rtx, rtx));
+ rtx_insn *(*)(rtx, rtx, rtx), rtx_insn *(*)(rtx, rtx, rtx));
extern bool loongarch_16b_atomic_lock_free_p (void);
/* Routines implemented in loongarch-c.c. */
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 2aa50a6c716..7ab35c8d108 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -9290,8 +9290,9 @@ loongarch_expand_vec_interleave (rtx target, rtx op0, rtx
op1, bool high_p)
void
loongarch_expand_vec_widen_hilo (rtx dest, rtx op1, rtx op2,
- bool high_p, rtx (*fn_even) (rtx, rtx, rtx),
- rtx (*fn_odd) (rtx, rtx, rtx))
+ bool high_p,
+ rtx_insn *(*fn_even) (rtx, rtx, rtx),
+ rtx_insn *(*fn_odd) (rtx, rtx, rtx))
{
machine_mode wmode = GET_MODE (dest);
machine_mode mode = GET_MODE (op1);
@@ -10497,7 +10498,7 @@ loongarch_expand_vector_init (rtx target, rtx vals)
/* Copy two elements of vals to target vector. */
typedef rtx (*loongarch_vec_repl2_fn) (rtx, rtx, rtx);
/* Insert scalar operands into the specified position of the vector. */
- typedef rtx (*loongarch_vec_set_fn) (rtx, rtx, rtx);
+ typedef rtx_insn *(*loongarch_vec_set_fn) (rtx, rtx, rtx);
/* Copy 64bit lowpart to highpart. */
typedef rtx (*loongarch_vec_mirror_fn) (rtx, rtx, rtx);
/* Merge lowpart and highpart into target. */
diff --git a/gcc/config/mips/loongson-mmi.md b/gcc/config/mips/loongson-mmi.md
index 33f4bfccc44..519f0065dd5 100644
--- a/gcc/config/mips/loongson-mmi.md
+++ b/gcc/config/mips/loongson-mmi.md
@@ -853,7 +853,7 @@
"TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI"
{
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
- mips_expand_vec_reduc (tmp, operands[1], gen_add<mode>3);
+ mips_expand_vec_reduc (tmp, operands[1], gen_insn_add<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
@@ -864,7 +864,7 @@
"TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI"
{
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
- mips_expand_vec_reduc (tmp, operands[1], gen_smax<mode>3);
+ mips_expand_vec_reduc (tmp, operands[1], gen_insn_smax<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
@@ -875,7 +875,7 @@
"TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI"
{
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
- mips_expand_vec_reduc (tmp, operands[1], gen_smin<mode>3);
+ mips_expand_vec_reduc (tmp, operands[1], gen_insn_smin<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
@@ -886,7 +886,7 @@
"TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI"
{
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
- mips_expand_vec_reduc (tmp, operands[1], gen_umax<mode>3);
+ mips_expand_vec_reduc (tmp, operands[1], gen_insn_umax<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
@@ -897,7 +897,7 @@
"TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI"
{
rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
- mips_expand_vec_reduc (tmp, operands[1], gen_umin<mode>3);
+ mips_expand_vec_reduc (tmp, operands[1], gen_insn_umin<mode>3);
emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
DONE;
})
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index d02d60c38e0..45dbd49de8f 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -351,7 +351,7 @@ extern void mips_expand_atomic_qihi (union mips_gen_fn_ptrs,
extern void mips_expand_vector_init (rtx, rtx);
extern void mips_expand_vec_unpack (rtx op[2], bool, bool);
-extern void mips_expand_vec_reduc (rtx, rtx, rtx (*)(rtx, rtx, rtx));
+extern void mips_expand_vec_reduc (rtx, rtx, rtx_insn *(*)(rtx, rtx, rtx));
extern void mips_expand_msa_reduc (rtx (*)(rtx, rtx, rtx), rtx, rtx);
extern void mips_expand_vec_minmax (rtx, rtx, rtx,
rtx (*) (rtx, rtx, rtx), bool);
@@ -380,7 +380,7 @@ extern int mips_trampoline_code_size (void);
extern void mips_function_profiler (FILE *);
extern bool mips_load_store_bonding_p (rtx *, machine_mode, bool);
-typedef rtx (*mulsidi3_gen_fn) (rtx, rtx, rtx);
+typedef rtx_insn *(*mulsidi3_gen_fn) (rtx, rtx, rtx);
#ifdef RTX_CODE
extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum rtx_code);
#endif
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4402ae17c0d..2c986faffd7 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -21286,16 +21286,16 @@ mips_mulsidi3_gen_fn (enum rtx_code ext_code)
ensure that we always remove the redundant sign-extension in this
case we still expand mulsidi3 for DMUL. */
if (ISA_HAS_R6DMUL)
- return signed_p ? gen_mulsidi3_64bit_r6dmul : NULL;
+ return signed_p ? gen_insn_mulsidi3_64bit_r6dmul : NULL;
if (ISA_HAS_DMUL3)
- return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
+ return signed_p ? gen_insn_mulsidi3_64bit_dmul : NULL;
if (TARGET_MIPS16)
return (signed_p
? gen_mulsidi3_64bit_mips16
: gen_umulsidi3_64bit_mips16);
if (TARGET_FIX_R4000)
return NULL;
- return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
+ return signed_p ? gen_insn_mulsidi3_64bit : gen_insn_umulsidi3_64bit;
}
else
{
@@ -21306,8 +21306,10 @@ mips_mulsidi3_gen_fn (enum rtx_code ext_code)
? gen_mulsidi3_32bit_mips16
: gen_umulsidi3_32bit_mips16);
if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
- return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
- return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
+ return (signed_p
+ ? gen_insn_mulsidi3_32bit_r4000
+ : gen_insn_umulsidi3_32bit_r4000);
+ return signed_p ? gen_insn_mulsidi3_32bit : gen_insn_umulsidi3_32bit;
}
}
@@ -22839,7 +22841,7 @@ mips_expand_vector_init (rtx target, rtx vals)
/* Expand a vector reduction. */
void
-mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
+mips_expand_vec_reduc (rtx target, rtx in, rtx_insn *(*gen)(rtx, rtx, rtx))
{
machine_mode vmode = GET_MODE (in);
unsigned char perm2[2];
diff --git a/gcc/config/rl78/rl78-protos.h b/gcc/config/rl78/rl78-protos.h
index b658e00b692..e4982349522 100644
--- a/gcc/config/rl78/rl78-protos.h
+++ b/gcc/config/rl78/rl78-protos.h
@@ -27,8 +27,8 @@ void rl78_expand_compare (rtx *);
void rl78_expand_movsi (rtx *);
void rl78_split_movsi (rtx *, machine_mode);
void rl78_split_movdi (rtx *, enum machine_mode);
-int rl78_force_nonfar_2 (rtx *, rtx (*gen)(rtx,rtx));
-int rl78_force_nonfar_3 (rtx *, rtx (*gen)(rtx,rtx,rtx));
+int rl78_force_nonfar_2 (rtx *, rtx_insn *(*gen)(rtx,rtx));
+int rl78_force_nonfar_3 (rtx *, rtx_insn *(*gen)(rtx,rtx,rtx));
void rl78_expand_eh_epilogue (rtx);
void rl78_expand_epilogue (void);
void rl78_expand_prologue (void);
diff --git a/gcc/config/rl78/rl78.cc b/gcc/config/rl78/rl78.cc
index 67fb86a1689..c073cfad658 100644
--- a/gcc/config/rl78/rl78.cc
+++ b/gcc/config/rl78/rl78.cc
@@ -623,7 +623,7 @@ rl78_split_movdi (rtx *operands, enum machine_mode omode)
operands in the "far" namespace. Force some such operands into
registers so that each pattern has at most one far operand. */
int
-rl78_force_nonfar_2 (rtx *operands, rtx (*gen)(rtx,rtx))
+rl78_force_nonfar_2 (rtx *operands, rtx_insn *(*gen)(rtx,rtx))
{
int did = 0;
rtx temp_reg = NULL;
@@ -648,7 +648,7 @@ rl78_force_nonfar_2 (rtx *operands, rtx (*gen)(rtx,rtx))
/* Likewise, but for three-operand expanders. */
int
-rl78_force_nonfar_3 (rtx *operands, rtx (*gen)(rtx,rtx,rtx))
+rl78_force_nonfar_3 (rtx *operands, rtx_insn *(*gen)(rtx,rtx,rtx))
{
int did = 0;
rtx temp_reg = NULL;
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 0fc4d6d3065..ba0e5a62af2 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2691,16 +2691,16 @@ expand_strn_compare (rtx operands[], int no_length)
DEST is the destination for the data.
SRC is the source of the data for the move. */
-static rtx
+static rtx_insn *
gen_lvx_v4si_move (rtx dest, rtx src)
{
gcc_assert (MEM_P (dest) ^ MEM_P (src));
gcc_assert (GET_MODE (dest) == V4SImode && GET_MODE (src) == V4SImode);
if (MEM_P (dest))
- return gen_altivec_stvx_v4si_internal (dest, src);
+ return gen_insn_altivec_stvx_v4si_internal (dest, src);
else
- return gen_altivec_lvx_v4si_internal (dest, src);
+ return gen_insn_altivec_lvx_v4si_internal (dest, src);
}
static rtx
@@ -2775,7 +2775,7 @@ expand_block_move (rtx operands[], bool might_overlap)
for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
{
union {
- rtx (*mov) (rtx, rtx);
+ rtx_insn *(*mov) (rtx, rtx);
rtx (*movlen) (rtx, rtx, int);
} gen_func;
machine_mode mode = BLKmode;
@@ -2804,7 +2804,7 @@ expand_block_move (rtx operands[], bool might_overlap)
{
move_bytes = 16;
mode = V2DImode;
- gen_func.mov = gen_vsx_movv2di_64bit;
+ gen_func.mov = gen_insn_vsx_movv2di_64bit;
}
else if (TARGET_BLOCK_OPS_UNALIGNED_VSX
/* Only use lxvl/stxvl on 64bit POWER10. */
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 023e5e42aab..8d2a6c0582c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7223,9 +7223,9 @@ rs6000_expand_vector_init (rtx target, rtx vals)
}
else
{
- rtx (*merge_v16qi) (rtx, rtx, rtx) = NULL;
- rtx (*merge_v8hi) (rtx, rtx, rtx) = NULL;
- rtx (*merge_v4si) (rtx, rtx, rtx) = NULL;
+ rtx_insn *(*merge_v16qi) (rtx, rtx, rtx) = NULL;
+ rtx_insn *(*merge_v8hi) (rtx, rtx, rtx) = NULL;
+ rtx_insn *(*merge_v4si) (rtx, rtx, rtx) = NULL;
rtx perm_idx;
/* Set up some common gen routines and values. */
@@ -7432,17 +7432,17 @@ rs6000_expand_vector_set_var_p7 (rtx target, rtx val,
rtx idx)
machine_mode shift_mode;
rtx (*gen_ashl)(rtx, rtx, rtx);
- rtx (*gen_add)(rtx, rtx, rtx);
- rtx (*gen_sub)(rtx, rtx, rtx);
- rtx (*gen_lvsl)(rtx, rtx);
+ rtx_insn *(*gen_add)(rtx, rtx, rtx);
+ rtx_insn *(*gen_sub)(rtx, rtx, rtx);
+ rtx_insn *(*gen_lvsl)(rtx, rtx);
if (TARGET_POWERPC64)
{
shift_mode = DImode;
gen_ashl = gen_ashldi3;
gen_add = gen_adddi3;
- gen_sub = gen_subdi3;
- gen_lvsl = gen_altivec_lvsl_reg_di;
+ gen_sub = gen_insn_subdi3;
+ gen_lvsl = gen_insn_altivec_lvsl_reg_di;
}
else
{
@@ -7450,7 +7450,7 @@ rs6000_expand_vector_set_var_p7 (rtx target, rtx val, rtx
idx)
gen_ashl = gen_ashlsi3;
gen_add = gen_addsi3;
gen_sub = gen_subsi3;
- gen_lvsl = gen_altivec_lvsl_reg_si;
+ gen_lvsl = gen_insn_altivec_lvsl_reg_si;
}
/* idx = idx * width. */
@@ -16937,26 +16937,26 @@ emit_unlikely_jump (rtx cond, rtx label)
static void
emit_load_locked (machine_mode mode, rtx reg, rtx mem, rtx local)
{
- rtx (*fn) (rtx, rtx, rtx) = NULL;
+ rtx_insn *(*fn) (rtx, rtx, rtx) = NULL;
switch (mode)
{
case E_QImode:
- fn = gen_load_lockedqi;
+ fn = gen_insn_load_lockedqi;
break;
case E_HImode:
- fn = gen_load_lockedhi;
+ fn = gen_insn_load_lockedhi;
break;
case E_SImode:
if (GET_MODE (mem) == QImode)
- fn = gen_load_lockedqi_si;
+ fn = gen_insn_load_lockedqi_si;
else if (GET_MODE (mem) == HImode)
- fn = gen_load_lockedhi_si;
+ fn = gen_insn_load_lockedhi_si;
else
- fn = gen_load_lockedsi;
+ fn = gen_insn_load_lockedsi;
break;
case E_DImode:
- fn = gen_load_lockeddi;
+ fn = gen_insn_load_lockeddi;
break;
case E_TImode:
fn = gen_load_lockedti;
@@ -16973,21 +16973,21 @@ emit_load_locked (machine_mode mode, rtx reg, rtx
mem, rtx local)
static void
emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
{
- rtx (*fn) (rtx, rtx, rtx) = NULL;
+ rtx_insn *(*fn) (rtx, rtx, rtx) = NULL;
switch (mode)
{
case E_QImode:
- fn = gen_store_conditionalqi;
+ fn = gen_insn_store_conditionalqi;
break;
case E_HImode:
- fn = gen_store_conditionalhi;
+ fn = gen_insn_store_conditionalhi;
break;
case E_SImode:
- fn = gen_store_conditionalsi;
+ fn = gen_insn_store_conditionalsi;
break;
case E_DImode:
- fn = gen_store_conditionaldi;
+ fn = gen_insn_store_conditionaldi;
break;
case E_TImode:
fn = gen_store_conditionalti;
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 9902daec371..de8a83a7767 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -11811,8 +11811,7 @@ save_gprs (rtx base, int offset, int first, int last,
rtx_insn *before = NULL)
/* Special-case single register. */
if (first == last)
{
- insn = as_a <rtx_insn *> (gen_movdi (addr,
- gen_rtx_REG (Pmode, first)));
+ insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
if (!global_not_special_regno_p (first))
RTX_FRAME_RELATED_P (insn) = 1;
@@ -11828,9 +11827,8 @@ save_gprs (rtx base, int offset, int first, int last,
rtx_insn *before = NULL)
}
- insn = as_a <rtx_insn *> (gen_store_multiple (addr,
- gen_rtx_REG (Pmode, first),
- GEN_INT (last - first + 1)));
+ insn = gen_store_multiple (addr, gen_rtx_REG (Pmode, first),
+ GEN_INT (last - first + 1));
if (first <= 6 && cfun->stdarg)
for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc
index bfc6cfad51f..98dd59d1aa2 100644
--- a/gcc/emit-rtl.cc
+++ b/gcc/emit-rtl.cc
@@ -4199,6 +4199,8 @@ make_insn_raw (rtx pattern)
rtx_insn *insn;
insn = as_a <rtx_insn *> (rtx_alloc (INSN));
+ SET_NEXT_INSN (insn) = nullptr;
+ SET_PREV_INSN (insn) = nullptr;
INSN_UID (insn) = cur_insn_uid++;
PATTERN (insn) = pattern;
@@ -4230,6 +4232,8 @@ make_debug_insn_raw (rtx pattern)
rtx_debug_insn *insn;
insn = as_a <rtx_debug_insn *> (rtx_alloc (DEBUG_INSN));
+ SET_NEXT_INSN (insn) = nullptr;
+ SET_PREV_INSN (insn) = nullptr;
INSN_UID (insn) = cur_debug_insn_uid++;
if (cur_debug_insn_uid > param_min_nondebug_insn_uid)
INSN_UID (insn) = cur_insn_uid++;
@@ -4245,12 +4249,14 @@ make_debug_insn_raw (rtx pattern)
/* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
-static rtx_insn *
+rtx_insn *
make_jump_insn_raw (rtx pattern)
{
rtx_jump_insn *insn;
insn = as_a <rtx_jump_insn *> (rtx_alloc (JUMP_INSN));
+ SET_NEXT_INSN (insn) = nullptr;
+ SET_PREV_INSN (insn) = nullptr;
INSN_UID (insn) = cur_insn_uid++;
PATTERN (insn) = pattern;
@@ -4265,12 +4271,14 @@ make_jump_insn_raw (rtx pattern)
/* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
-static rtx_insn *
+rtx_insn *
make_call_insn_raw (rtx pattern)
{
rtx_call_insn *insn;
insn = as_a <rtx_call_insn *> (rtx_alloc (CALL_INSN));
+ SET_NEXT_INSN (insn) = nullptr;
+ SET_PREV_INSN (insn) = nullptr;
INSN_UID (insn) = cur_insn_uid++;
PATTERN (insn) = pattern;
diff --git a/gcc/genemit.cc b/gcc/genemit.cc
index c40f7fc7fb1..ee5961f1e46 100644
--- a/gcc/genemit.cc
+++ b/gcc/genemit.cc
@@ -411,9 +411,10 @@ maybe_queue_insn (const md_rtx_info &info)
in STATS. Return the C++ expression for the operands array. */
static const char *
-start_gen_insn (FILE *file, const char *name, const pattern_stats &stats)
+start_gen_insn (FILE *file, const char *name, const pattern_stats &stats,
+ bool return_pat)
{
- fprintf (file, "rtx\ngen_%s (", name);
+ fprintf (file, "%s\ngen_%s (", return_pat ? "rtx" : "rtx_insn *", name);
if (stats.num_generator_args)
for (int i = 0; i < stats.num_generator_args; i++)
fprintf (file, "%sconst rtx operand%d", i == 0 ? "" : ", ", i);
@@ -441,6 +442,33 @@ start_gen_insn (FILE *file, const char *name, const
pattern_stats &stats)
return "nullptr";
}
+/* Generate an rtx_insn * gen_insn_<name> wrapper around gen_<name>.
+ MAKE_INSN is make_insn_raw, make_jump_insn_raw, or make_call_insn_raw.
+ The insn is not inserted into the current sequence. */
+
+static void
+gen_insn_wrapper (FILE *file, const char *name, int args,
+ const char *make_insn)
+{
+ int i;
+
+ fprintf (file, "rtx_insn *\ngen_insn_%s (", name);
+ if (args > 0)
+ {
+ for (i = 1; i < args; i++)
+ fprintf (file, "rtx %c, ", 'a' + i - 1);
+ fprintf (file, "rtx %c", 'a' + args - 1);
+ }
+ fprintf (file, ")\n{ return %s (gen_%s (", make_insn, name);
+ if (args > 0)
+ {
+ for (i = 1; i < args; i++)
+ fprintf (file, "%c, ", 'a' + i - 1);
+ fprintf (file, "%c", 'a' + args - 1);
+ }
+ fprintf (file, ")); }\n");
+}
+
/* Generate the `gen_...' function for a DEFINE_INSN. */
static void
@@ -455,13 +483,16 @@ gen_insn (const md_rtx_info &info, FILE *file)
fatal_at (info.loc, "match_dup operand number has no match_operand");
/* Output the function name and argument declarations. */
- const char *operands = start_gen_insn (file, XSTR (insn, 0), stats);
+ const char *operands = start_gen_insn (file, XSTR (insn, 0), stats,
+ true);
/* Output code to construct and return the rtl for the instruction body. */
rtx pattern = add_implicit_parallel (XVEC (insn, 1));
const char *table = generator (info).gen_exp (file, pattern);
fprintf (file, " return expand_rtx (%s, %s);\n}\n\n", table, operands);
+ gen_insn_wrapper (file, XSTR (insn, 0), stats.num_generator_args,
+ get_make_insn_function (pattern));
}
/* Process and queue the DEFINE_EXPAND in INFO. */
@@ -493,19 +524,23 @@ gen_expand (const md_rtx_info &info, FILE *file)
fatal_at (info.loc, "define_expand for %s needs to have match_scratch "
"numbers above all other operands", XSTR (expand, 0));
+ /* A one-element expand with no C code returns the pattern, like a
+ DEFINE_INSN. Anything that emits insns returns an rtx_insn *. */
+ bool return_pat = ((XSTR (expand, 3) == 0 || *XSTR (expand, 3) == '\0')
+ && stats.max_opno >= stats.max_dup_opno
+ && XVECLEN (expand, 1) == 1);
+
/* Output the function name and argument declarations. */
- const char *operands = start_gen_insn (file, XSTR (expand, 0), stats);
-
- /* If we don't have any C code to write, only one insn is being written,
- and no MATCH_DUPs are present, we can just return the desired insn
- like we do for a DEFINE_INSN. This saves memory. */
- if ((XSTR (expand, 3) == 0 || *XSTR (expand, 3) == '\0')
- && stats.max_opno >= stats.max_dup_opno
- && XVECLEN (expand, 1) == 1)
+ const char *operands = start_gen_insn (file, XSTR (expand, 0), stats,
+ return_pat);
+
+ if (return_pat)
{
rtx pattern = XVECEXP (expand, 1, 0);
const char *table = generator (info).gen_exp (file, pattern);
fprintf (file, " return expand_rtx (%s, %s);\n}\n\n", table, operands);
+ gen_insn_wrapper (file, XSTR (expand, 0), stats.num_generator_args,
+ get_make_insn_function (pattern));
return;
}
diff --git a/gcc/genflags.cc b/gcc/genflags.cc
index 8b917144119..ab672ce48fb 100644
--- a/gcc/genflags.cc
+++ b/gcc/genflags.cc
@@ -102,11 +102,22 @@ gen_proto (rtx insn)
int i;
const char *name = XSTR (insn, 0);
int truth = maybe_eval_c_test (XSTR (insn, 2));
+ pattern_stats stats;
+ get_pattern_stats (&stats, XVEC (insn, 1));
+ /* DEFINE_INSN, and a one-element define_expand with no C code,
+ return the pattern. An expand that emits insns returns an
+ rtx_insn *. */
+ bool return_pat = (GET_CODE (insn) == DEFINE_INSN
+ || ((!XSTR (insn, 3) || XSTR (insn, 3)[0] == '\0')
+ && stats.max_opno >= stats.max_dup_opno
+ && XVECLEN (insn, 1) == 1));
+ const char *ret_type = return_pat ? "rtx" : "rtx_insn *";
if (truth != 0)
- printf ("extern rtx gen_%-*s (", max_id_len, name);
+ printf ("extern %s gen_%-*s (", ret_type, max_id_len, name);
else
- printf ("static inline rtx gen_%-*s (", max_id_len, name);
+ printf ("static inline %s gen_%-*s (", ret_type, max_id_len,
+ name);
if (num == 0)
fputs ("void", stdout);
@@ -120,11 +131,59 @@ gen_proto (rtx insn)
puts (");");
+ if (return_pat)
+ {
+ /* genemit drops an elided pattern, so the wrapper is a stub. */
+ if (truth == 0)
+ {
+ printf ("static inline rtx_insn *\ngen_insn_%s", name);
+ if (num > 0)
+ {
+ putchar ('(');
+ for (i = 0; i < num - 1; i++)
+ printf ("rtx ARG_UNUSED (%c), ", 'a' + i);
+ printf ("rtx ARG_UNUSED (%c))\n", 'a' + i);
+ }
+ else
+ puts ("(void)");
+ puts ("{\n return 0;\n}");
+ }
+ else
+ {
+ printf ("extern rtx_insn *gen_insn_%s (", name);
+ if (num > 0)
+ {
+ for (i = 1; i < num; i++)
+ printf ("rtx, ");
+ printf ("rtx");
+ }
+ puts (");");
+ }
+ }
+ else
+ {
+ printf ("static inline rtx_insn *\ngen_insn_%s (", name);
+ if (num > 0)
+ {
+ for (i = 1; i < num; i++)
+ printf ("rtx %c, ", 'a' + i - 1);
+ printf ("rtx %c", 'a' + i - 1);
+ }
+ printf (")\n{ return gen_%s (", name);
+ if (num > 0)
+ {
+ for (i = 1; i < num; i++)
+ printf ("%c, ", 'a' + i - 1);
+ printf ("%c", 'a' + i - 1);
+ }
+ printf ("); }\n");
+ }
+
/* Some back ends want to take the address of generator functions,
so we cannot simply use #define for these dummy definitions. */
if (truth == 0)
{
- printf ("static inline rtx\ngen_%s", name);
+ printf ("static inline %s\ngen_%s", ret_type, name);
if (num > 0)
{
putchar ('(');
diff --git a/gcc/gensupport.cc b/gcc/gensupport.cc
index 0bacafc848b..ab0dba08f96 100644
--- a/gcc/gensupport.cc
+++ b/gcc/gensupport.cc
@@ -3751,23 +3751,22 @@ get_pattern_stats (struct pattern_stats *stats, rtvec
pattern)
stats->max_scratch_opno)) + 1;
}
-/* Return the emit_* function that should be used for pattern X, or NULL
- if we can't pick a particular type at compile time and should instead
- fall back to "emit". */
+/* Return the make_*_insn_raw function for pattern X, or NULL if the
+ insn code is only known when the compiler is run. */
const char *
-get_emit_function (rtx x)
+get_make_insn_function (rtx x)
{
switch (classify_insn (x))
{
case INSN:
- return "emit_insn";
+ return "make_insn_raw";
case CALL_INSN:
- return "emit_call_insn";
+ return "make_call_insn_raw";
case JUMP_INSN:
- return "emit_jump_insn";
+ return "make_jump_insn_raw";
case UNKNOWN:
return NULL;
diff --git a/gcc/gensupport.h b/gcc/gensupport.h
index 880505355b2..8eab8f533fd 100644
--- a/gcc/gensupport.h
+++ b/gcc/gensupport.h
@@ -230,7 +230,7 @@ extern hash_set<rtx> compact_syntax;
extern void get_pattern_stats (struct pattern_stats *ranges, rtvec vec);
extern void compute_test_codes (rtx, file_location, char *);
extern file_location get_file_location (rtx);
-extern const char *get_emit_function (rtx);
+extern const char *get_make_insn_function (rtx);
extern bool find_optab (optab_pattern *, const char *);
/* An output file produced by a machine-description generator. Partition
diff --git a/gcc/rtl.cc b/gcc/rtl.cc
index dac230b2159..f7ed0de9295 100644
--- a/gcc/rtl.cc
+++ b/gcc/rtl.cc
@@ -31,6 +31,7 @@ along with GCC; see the file COPYING3. If not see
#include "rtl.h"
#ifdef GENERATOR_FILE
# include "errors.h"
+# include "gensupport.h"
#else
# include "rtlhash.h"
# include "diagnostic-core.h"
@@ -606,6 +607,70 @@ rtvec_series_p (rtvec vec, poly_int64 start)
return true;
}
+/* Classify the elements of VEC. VEC is either the body of a PARALLEL
+ or the required prefix of a MATCH_PARALLEL. A call or return that
+ selects CALL_INSN or JUMP_INSN is one of those elements. */
+
+static enum rtx_code
+classify_insn_vec (rtvec vec)
+{
+ int j;
+ bool has_return_p = false;
+
+ for (j = GET_NUM_ELEM (vec) - 1; j >= 0; j--)
+ {
+ rtx el = RTVEC_ELT (vec, j);
+
+ if (GET_CODE (el) == CALL)
+ return CALL_INSN;
+ else if (ANY_RETURN_P (el))
+ has_return_p = true;
+ else if (GET_CODE (el) == SET && GET_CODE (SET_DEST (el)) == PC)
+ return JUMP_INSN;
+ else if (GET_CODE (el) == SET && GET_CODE (SET_SRC (el)) == CALL)
+ return CALL_INSN;
+ }
+ if (has_return_p)
+ return JUMP_INSN;
+ if (GET_NUM_ELEM (vec) > 0
+ && GET_CODE (RTVEC_ELT (vec, 0)) == ASM_OPERANDS
+ && ASM_OPERANDS_LABEL_LENGTH (RTVEC_ELT (vec, 0)))
+ return JUMP_INSN;
+ return INSN;
+}
+
+#ifdef GENERATOR_FILE
+/* True when every code PRED accepts is an ordinary insn body. A call,
+ set, parallel, return, or asm can still select another insn code. */
+
+static bool
+predicate_is_always_insn (const struct pred_data *pred)
+{
+ if (!pred || pred->num_codes == 0)
+ return false;
+
+ for (int code = 0; code < NUM_RTX_CODE; code++)
+ if (pred->codes[code])
+ switch ((enum rtx_code) code)
+ {
+ case CALL:
+ case SET:
+ case PARALLEL:
+ case RETURN:
+ case SIMPLE_RETURN:
+ case ASM_OPERANDS:
+ case ASM_INPUT:
+ case CODE_LABEL:
+ return false;
+
+ default:
+ break;
+ }
+
+ return true;
+}
+#endif
+
/* Return an indication of which type of insn should have X as a body.
In generator files, this can be UNKNOWN if the answer is only known
at (GCC) runtime. Otherwise the value is CODE_LABEL, INSN, CALL_INSN
@@ -632,33 +697,19 @@ classify_insn (rtx x)
return INSN;
}
if (GET_CODE (x) == PARALLEL)
- {
- int j;
- bool has_return_p = false;
- for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
- if (GET_CODE (XVECEXP (x, 0, j)) == CALL)
- return CALL_INSN;
- else if (ANY_RETURN_P (XVECEXP (x, 0, j)))
- has_return_p = true;
- else if (GET_CODE (XVECEXP (x, 0, j)) == SET
- && GET_CODE (SET_DEST (XVECEXP (x, 0, j))) == PC)
- return JUMP_INSN;
- else if (GET_CODE (XVECEXP (x, 0, j)) == SET
- && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL)
- return CALL_INSN;
- if (has_return_p)
- return JUMP_INSN;
- if (GET_CODE (XVECEXP (x, 0, 0)) == ASM_OPERANDS
- && ASM_OPERANDS_LABEL_LENGTH (XVECEXP (x, 0, 0)))
- return JUMP_INSN;
- }
+ return classify_insn_vec (XVEC (x, 0));
#ifdef GENERATOR_FILE
+ /* The predicate may accept elements past this prefix. The RTX that
+ selects the insn code is written in the prefix. */
+ if (GET_CODE (x) == MATCH_PARALLEL)
+ return classify_insn_vec (XVEC (x, 2));
+ if (GET_CODE (x) == MATCH_OPERAND
+ && predicate_is_always_insn (lookup_predicate (XSTR (x, 1))))
+ return INSN;
if (GET_CODE (x) == MATCH_OPERAND
|| GET_CODE (x) == MATCH_OPERATOR
- || GET_CODE (x) == MATCH_PARALLEL
|| GET_CODE (x) == MATCH_OP_DUP
- || GET_CODE (x) == MATCH_DUP
- || GET_CODE (x) == PARALLEL)
+ || GET_CODE (x) == MATCH_DUP)
return UNKNOWN;
#endif
return INSN;
diff --git a/gcc/rtl.h b/gcc/rtl.h
index d4ba485feb9..53fa353fb0b 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -3494,6 +3494,8 @@ extern rtx_insn *emit_clobber (rtx);
extern rtx_insn *gen_use (rtx);
extern rtx_insn *emit_use (rtx);
extern rtx_insn *make_insn_raw (rtx);
+extern rtx_insn *make_jump_insn_raw (rtx);
+extern rtx_insn *make_call_insn_raw (rtx);
extern void add_function_usage_to (rtx_insn *, rtx);
extern rtx_call_insn *last_call_insn (void);
extern rtx_insn *previous_insn (rtx_insn *);
--
2.53.0
