Floating-point min/max instructions currently use the "fmove" type, so a
pipeline description cannot give them a latency different from a register
move. Add a separate "fminmax" insn type and use it for the fmin/fmax
patterns. Every existing scheduling model that reserved "fmove" now
reserves "fminmax" in the same way, so current scheduling does not change.
gcc/ChangeLog:
* config/riscv/riscv.md (type): Add fminmax.
(fminm<mode>3, fmaxm<mode>3, fmin<mode>3, fmax<mode>3)
(smin<mode>3, smax<mode>3): Use fminmax type.
* config/riscv/andes-23-series.md (andes_23_fpu_move): Add fminmax.
* config/riscv/andes-25-series.md (andes_25_fpu_move): Likewise.
* config/riscv/andes-45-series.md (andes_45_fpu_move): Likewise.
* config/riscv/arcv-rhx100.md (arcv_rhx100_xfer): Likewise.
* config/riscv/arcv-rmx100.md (arcv_rmx100_xfer): Likewise.
* config/riscv/generic-ooo.md (generic_ooo_float_move): Likewise.
* config/riscv/generic.md (generic_xfer): Likewise.
* config/riscv/mips-p8700.md (mips_p8700_fpu_fabs): Likewise.
* config/riscv/sifive-7.md (sifive_7_fp_other): Likewise.
* config/riscv/sifive-p400.md (sifive_p400_fmove): Likewise.
* config/riscv/sifive-p600.md (sifive_p600_fmove): Likewise.
* config/riscv/spacemit-x60.md (spacemit_x60_fcvt): Likewise.
* config/riscv/tt-ascalon-d8.md (tt_ascalon_d8_float_move): Likewise.
* config/riscv/xiangshan.md (xiangshan_f2f): Likewise.
* config/riscv/xt-c908.md (xt_c908_fcvt): Likewise.
Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
---
gcc/config/riscv/andes-23-series.md | 2 +-
gcc/config/riscv/andes-25-series.md | 2 +-
gcc/config/riscv/andes-45-series.md | 2 +-
gcc/config/riscv/arcv-rhx100.md | 2 +-
gcc/config/riscv/arcv-rmx100.md | 2 +-
gcc/config/riscv/generic-ooo.md | 2 +-
gcc/config/riscv/generic.md | 2 +-
gcc/config/riscv/mips-p8700.md | 2 +-
gcc/config/riscv/riscv.md | 19 ++++++++++---------
gcc/config/riscv/sifive-7.md | 2 +-
gcc/config/riscv/sifive-p400.md | 2 +-
gcc/config/riscv/sifive-p600.md | 2 +-
gcc/config/riscv/spacemit-x60.md | 2 +-
gcc/config/riscv/tt-ascalon-d8.md | 2 +-
gcc/config/riscv/xiangshan.md | 2 +-
gcc/config/riscv/xt-c908.md | 2 +-
16 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/gcc/config/riscv/andes-23-series.md
b/gcc/config/riscv/andes-23-series.md
index f0f0a44f713..02259294324 100644
--- a/gcc/config/riscv/andes-23-series.md
+++ b/gcc/config/riscv/andes-23-series.md
@@ -112,7 +112,7 @@
(define_insn_reservation "andes_23_fpu_move" 2
(and (eq_attr "tune" "andes_23_series")
- (eq_attr "type" "fmove,mtc,mfc"))
+ (eq_attr "type" "fmove,fminmax,mtc,mfc"))
"andes_23_pipe_unify, andes_23_fpu")
(define_insn_reservation "andes_23_fpu_cmp" 3
diff --git a/gcc/config/riscv/andes-25-series.md
b/gcc/config/riscv/andes-25-series.md
index c11fe16d6e4..596876f1d25 100644
--- a/gcc/config/riscv/andes-25-series.md
+++ b/gcc/config/riscv/andes-25-series.md
@@ -128,7 +128,7 @@
(define_insn_reservation "andes_25_fpu_move" 3
(and (eq_attr "tune" "andes_25_series")
- (eq_attr "type" "fmove,mtc,mfc"))
+ (eq_attr "type" "fmove,fminmax,mtc,mfc"))
"andes_25_fpu_pipe")
(define_insn_reservation "andes_25_fpu_cmp" 3
diff --git a/gcc/config/riscv/andes-45-series.md
b/gcc/config/riscv/andes-45-series.md
index 4e3cf79dbe8..9c08ee2d90a 100644
--- a/gcc/config/riscv/andes-45-series.md
+++ b/gcc/config/riscv/andes-45-series.md
@@ -157,7 +157,7 @@
(define_insn_reservation "andes_45_fpu_move" 1
(and (eq_attr "tune" "andes_45_series")
- (eq_attr "type" "fmove,mtc,mfc"))
+ (eq_attr "type" "fmove,fminmax,mtc,mfc"))
"andes_45_pipe0 + andes_45_fpu_fmv | andes_45_pipe1 + andes_45_fpu_fmv")
(define_insn_reservation "andes_45_fpu_cmp" 2
diff --git a/gcc/config/riscv/arcv-rhx100.md b/gcc/config/riscv/arcv-rhx100.md
index 72f0147ea36..9433ff4f1ba 100644
--- a/gcc/config/riscv/arcv-rhx100.md
+++ b/gcc/config/riscv/arcv-rhx100.md
@@ -87,7 +87,7 @@
;; (soft) floating points
(define_insn_reservation "arcv_rhx100_xfer" 3
(and (eq_attr "tune" "arcv_rhx100,arcv_rpx100")
- (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
+ (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fminmax,fcmp"))
"(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early)")
(define_insn_reservation "arcv_rhx100_fmul" 5
diff --git a/gcc/config/riscv/arcv-rmx100.md b/gcc/config/riscv/arcv-rmx100.md
index e786cbb3ee4..593036b0245 100644
--- a/gcc/config/riscv/arcv-rmx100.md
+++ b/gcc/config/riscv/arcv-rmx100.md
@@ -70,7 +70,7 @@
(define_insn_reservation "arcv_rmx100_xfer" 1
(and (eq_attr "tune" "arcv_rmx100")
- (eq_attr "type" "fmove,mtc,mfc,fcvt,fcvt_f2i,fcvt_i2f"))
+ (eq_attr "type" "fmove,fminmax,mtc,mfc,fcvt,fcvt_f2i,fcvt_i2f"))
"arcv_rmx100_FPU")
(define_insn_reservation "arcv_rmx100_fmul_insn" 2
diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 7ff05b7accf..f4607d27638 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -105,7 +105,7 @@
;; Float move, convert and compare.
(define_insn_reservation "generic_ooo_float_move" 3
(and (eq_attr "tune" "generic_ooo")
- (eq_attr "type" "fmove"))
+ (eq_attr "type" "fmove,fminmax"))
"generic_ooo_issue,generic_ooo_fxu")
(define_insn_reservation "generic_ooo_fcvt" 3
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index e286bc7f9c3..78d4b933e1d 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -44,7 +44,7 @@
(define_insn_reservation "generic_xfer" 3
(and (eq_attr "tune" "generic")
- (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
+ (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fminmax,fcmp"))
"alu")
(define_insn_reservation "generic_branch" 1
diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md
index bccdb6c6a0d..2f1574c880e 100644
--- a/gcc/config/riscv/mips-p8700.md
+++ b/gcc/config/riscv/mips-p8700.md
@@ -56,7 +56,7 @@
(define_insn_reservation "mips_p8700_fpu_fabs" 2
(and (eq_attr "tune" "mips_p8700")
- (eq_attr "type" "fcmp,fmove"))
+ (eq_attr "type" "fcmp,fmove,fminmax"))
"mips_p8700_fpu_short, mips_p8700_fpu_apu")
(define_insn_reservation "mips_p8700_fpu_fload" 8
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index bc8e7106e52..24e1fc845e7 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -332,6 +332,7 @@
;; idiv integer divide
;; move integer register move (addi rd, rs1, 0)
;; fmove floating point register move
+;; fminmax floating point min/max
;; fadd floating point add/subtract
;; fmul floating point multiply
;; fmadd floating point multiply-add
@@ -503,9 +504,9 @@
;; xt_vilo vector odd interleave instruction
(define_attr "type"
"unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore,
- mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
- fmadd,fdiv,fcmp,fcvt,fcvt_i2f,fcvt_f2i,fsqrt,multi,auipc,sfb_alu,nop,trap,
- ghost,bitmanip,rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
+ mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fminmax,
+ fadd,fmul,fmadd,fdiv,fcmp,fcvt,fcvt_i2f,fcvt_f2i,fsqrt,multi,auipc,sfb_alu,
+ nop,trap,ghost,bitmanip,rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
atomic,condmove,crypto,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,
rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
@@ -1661,7 +1662,7 @@
UNSPEC_FMINM))]
"TARGET_HARD_FLOAT && TARGET_ZFA"
"fminm.<fmt>\t%0,%1,%2"
- [(set_attr "type" "fmove")
+ [(set_attr "type" "fminmax")
(set_attr "mode" "<UNITMODE>")])
(define_insn "fmaxm<mode>3"
@@ -1671,7 +1672,7 @@
UNSPEC_FMAXM))]
"TARGET_HARD_FLOAT && TARGET_ZFA"
"fmaxm.<fmt>\t%0,%1,%2"
- [(set_attr "type" "fmove")
+ [(set_attr "type" "fminmax")
(set_attr "mode" "<UNITMODE>")])
(define_insn "fmin<mode>3"
@@ -1681,7 +1682,7 @@
UNSPEC_FMIN))]
"(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)"
"fmin.<fmt>\t%0,%1,%2"
- [(set_attr "type" "fmove")
+ [(set_attr "type" "fminmax")
(set_attr "mode" "<UNITMODE>")])
(define_insn "fmax<mode>3"
@@ -1691,7 +1692,7 @@
UNSPEC_FMAX))]
"(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)"
"fmax.<fmt>\t%0,%1,%2"
- [(set_attr "type" "fmove")
+ [(set_attr "type" "fminmax")
(set_attr "mode" "<UNITMODE>")])
(define_insn "smin<mode>3"
@@ -1700,7 +1701,7 @@
(match_operand:ANYF 2 "register_operand" " f")))]
"TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmin.<fmt>\t%0,%1,%2"
- [(set_attr "type" "fmove")
+ [(set_attr "type" "fminmax")
(set_attr "mode" "<UNITMODE>")])
(define_insn "smax<mode>3"
@@ -1709,7 +1710,7 @@
(match_operand:ANYF 2 "register_operand" " f")))]
"TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmax.<fmt>\t%0,%1,%2"
- [(set_attr "type" "fmove")
+ [(set_attr "type" "fminmax")
(set_attr "mode" "<UNITMODE>")])
;;
diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index 2ba25a62b4a..0e447179922 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -101,7 +101,7 @@
(define_insn_reservation "sifive_7_fp_other" 3
(and (eq_attr "tune" "sifive_7")
- (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i,fcmp,fmove"))
+ (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i,fcmp,fmove,fminmax"))
"sifive_7_B")
(define_insn_reservation "sifive_7_fdiv_h" 14
diff --git a/gcc/config/riscv/sifive-p400.md b/gcc/config/riscv/sifive-p400.md
index a859a81f635..f2b22c1c702 100644
--- a/gcc/config/riscv/sifive-p400.md
+++ b/gcc/config/riscv/sifive-p400.md
@@ -150,7 +150,7 @@
(define_insn_reservation "sifive_p400_fmove" 2
(and (eq_attr "tune" "sifive_p400")
- (eq_attr "type" "fmove,fcvt"))
+ (eq_attr "type" "fmove,fminmax,fcvt"))
"p400_float_pipe,sifive_p400_fpu")
;; We need something for HF so that we don't abort during
diff --git a/gcc/config/riscv/sifive-p600.md b/gcc/config/riscv/sifive-p600.md
index c4d9c577436..91d80e2b768 100644
--- a/gcc/config/riscv/sifive-p600.md
+++ b/gcc/config/riscv/sifive-p600.md
@@ -154,7 +154,7 @@
(define_insn_reservation "sifive_p600_fmove" 2
(and (eq_attr "tune" "sifive_p600")
- (eq_attr "type" "fmove,fcvt"))
+ (eq_attr "type" "fmove,fminmax,fcvt"))
"float_pipe,sifive_p600_fpu")
;; We need something for HF so that we don't abort during
diff --git a/gcc/config/riscv/spacemit-x60.md b/gcc/config/riscv/spacemit-x60.md
index f34d358c891..5d9370a0c26 100644
--- a/gcc/config/riscv/spacemit-x60.md
+++ b/gcc/config/riscv/spacemit-x60.md
@@ -130,7 +130,7 @@
(define_insn_reservation "spacemit_x60_fcvt" 4
(and (eq_attr "tune" "spacemit_x60")
- (eq_attr "type" "fcvt,fmove"))
+ (eq_attr "type" "fcvt,fmove,fminmax"))
"spacemit_x60_fpalu")
(define_insn_reservation "spacemit_x60_fcmp" 6
diff --git a/gcc/config/riscv/tt-ascalon-d8.md
b/gcc/config/riscv/tt-ascalon-d8.md
index 7bcadb16e4a..f5866acad70 100644
--- a/gcc/config/riscv/tt-ascalon-d8.md
+++ b/gcc/config/riscv/tt-ascalon-d8.md
@@ -75,7 +75,7 @@
;; are executed by the FPU, but we can't model that at the moment.
(define_insn_reservation "tt_ascalon_d8_float_move" 4
(and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
- (eq_attr "type" "fmove"))
+ (eq_attr "type" "fmove,fminmax"))
"tt_ascalon_d8_decode,tt_ascalon_d8_fp")
(define_insn_reservation "tt_ascalon_d8_fcvt" 3
diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md
index b15e845b381..bcf7de00cfd 100644
--- a/gcc/config/riscv/xiangshan.md
+++ b/gcc/config/riscv/xiangshan.md
@@ -133,7 +133,7 @@
(define_insn_reservation "xiangshan_f2f" 3
(and (eq_attr "tune" "xiangshan")
- (eq_attr "type" "fcvt,fcvt_f2i,fmove"))
+ (eq_attr "type" "fcvt,fcvt_f2i,fmove,fminmax"))
"xs_fmisc_rs")
(define_insn_reservation "xiangshan_f2i" 3
diff --git a/gcc/config/riscv/xt-c908.md b/gcc/config/riscv/xt-c908.md
index 32e4ad21ae9..aaabd387f09 100644
--- a/gcc/config/riscv/xt-c908.md
+++ b/gcc/config/riscv/xt-c908.md
@@ -69,7 +69,7 @@
(define_insn_reservation "xt_c908_fcvt" 4
(and (eq_attr "tune" "xt_c908")
- (eq_attr "type" "fcvt,fmove,fcvt_i2f,fcvt_f2i"))
+ (eq_attr "type" "fcvt,fmove,fminmax,fcvt_i2f,fcvt_f2i"))
"xt_c908_fpalu")
(define_insn_reservation "xt_c908_fcmp" 4
--
2.52.0
