Hi all,
This patch adds support for the AArch32 vmaxnm and vminnm VFP instructions
in that can be used to implement the smax[sf,df]3 and smin[sf,df]3 RTL
patterns.
The patterns are only used by gcc when unsafe math optimisations are turned
on.
Two new values for the type attribute are introduced: f_minmaxs and
f_minmaxd.
New compilation tests are added. They pass and no regressions on
arm-none-eabi.
Ok for trunk?
Thanks,
Kyrill
gcc/ChangeLog
2012-11-26 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/arm.md (f_minmaxs, f_minmaxd): New types.
* config/arm/vfp.md (smax<mode>3): New pattern.
(smin<mode>3): Likewise.
gcc/testsuite/ChangeLog
2012-11-26 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* gcc.target/arm/vmaxnmdf.c: New test.
* gcc.target/arm/vmaxnmsf.c: Likewise.
* gcc.target/arm/vminnmsf.c: Likewise.
* gcc.target/arm/vminnmdf.c: Likewise.--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -274,6 +274,8 @@
fmacd,\
f_rints,\
f_rintd,\
+ f_minmaxs,\
+ f_minmaxd,\
f_flag,\
f_loads,\
f_loadd,\
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 480a88d..82b277a 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1263,6 +1263,31 @@
(set_attr "type" "f_rint<vfp_type>")]
)
+;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
+;; The 'smax' and 'smin' RTL standard pattern names do not specify which
+;; operand will be returned when both operands are zero (i.e. they may not
+;; honour signed zeroes), or when either operand is NaN. Therefore GCC
+;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring
+;; NaNs.
+
+(define_insn "smax<mode>3"
+ [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+ (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
+ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+ "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+ [(set_attr "type" "f_minmax<vfp_type>")]
+)
+
+(define_insn "smin<mode>3"
+ [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+ (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
+ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+ "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+ [(set_attr "type" "f_minmax<vfp_type>")]
+)
+
;; Unimplemented insns:
;; fldm*
;; fstm*
diff --git a/gcc/testsuite/gcc.target/arm/vmaxnmdf.c
b/gcc/testsuite/gcc.target/arm/vmaxnmdf.c
new file mode 100644
index 0000000..1a172b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vmaxnmdf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+ return __builtin_fmax (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/vmaxnmsf.c
b/gcc/testsuite/gcc.target/arm/vmaxnmsf.c
new file mode 100644
index 0000000..bc23261
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vmaxnmsf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+ return __builtin_fmaxf (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/vminnmdf.c
b/gcc/testsuite/gcc.target/arm/vminnmdf.c
new file mode 100644
index 0000000..c2a6915
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vminnmdf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+ return __builtin_fmin (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/vminnmsf.c
b/gcc/testsuite/gcc.target/arm/vminnmsf.c
new file mode 100644
index 0000000..eee43bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vminnmsf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+ return __builtin_fminf (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+" 1 } } */
