Re: [PATCH, AArch64] Make zero_extends explicit for common SImode patterns

[Richard Earnshaw]

On 14/12/12 11:59, Ian Bolton wrote:
Hi Richard,
+  "add\\t%w0, %w2, %w, <su>xt<SHORT:size>"

                      ^^^ %w1

Got spot. I guess that pattern hasn't fired yet then!  I'll fix it.

Now fixed in v3.

I should have said that I am indeed running with REE enabled.  It has
some impact (about 70 further UXTW removed from the set of binaries
I've been building) and seems to mostly be good across basic blocks
within the same function.  As far as I can tell, there is no downside
to REE, so I think it should be enabled by default for O2 or higher
on AArch64 too.


I'm going to enable REE in a separate patch.

Is this one OK to commit here and backport to ARM/aarch64-4.7-branch?

Thanks,
Ian


Please can you fix up the indentation.  You've copied a lot of patterns 
and made the code changes, but then left the indetation inconsitent.

For example:

;; zero_extend version of above
(define_insn "*add_<shift>_si_uxtw"
  [(set (match_operand:DI 0 "register_operand" "=rk")
        (zero_extend:DI (plus:SI
           (ASHIFT:SI (match_operand:SI 1 "register_operand" "r")
                       (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
           (match_operand:SI 3 "register_operand" "r"))))]
  ""
  "add\\t%w0, %w3, %w1, <shift> %2"
  [(set_attr "v8type" "alu_shift")
   (set_attr "mode" "SI")]
)

Should be reformatted to:

;; zero_extend version of above
(define_insn "*add_<shift>_si_uxtw"
  [(set (match_operand:DI 0 "register_operand" "=rk")
        (zero_extend:DI
         (plus:SI
          (ASHIFT:SI (match_operand:SI 1 "register_operand" "r")
                     (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
          (match_operand:SI 3 "register_operand" "r"))))]
  ""
  "add\\t%w0, %w3, %w1, <shift> %2"
  [(set_attr "v8type" "alu_shift")
   (set_attr "mode" "SI")]
)

Which makes the association of operands much clearer.

OK with that change.

R.