I did changes. Please take a look.
2012/12/29, Uros Bizjak <ubiz...@gmail.com>:
> On Sat, Dec 29, 2012 at 6:26 AM, Vladimir Yakovlev <vbyakov...@gmail.com>
> wrote:
>
>> processor_alias_table contains the same processor type for all
>> "corei7", "corei7-avx", "core-avx-i" and "core-avx2". At least, it has
>> consequence on checking x86_avx256_split_unaligned_load &
>> ix86_tune_mask: for all these processors it results the same. Moreover
>> we cannot turn new features on for AVX/AVX2 using
>> initial_ix86_tune_features.
>
> corei7, corei7-avx and core-avx-i are all based on sandybridge (=
> PROCESSOR_COREI7) architecture. The only problematic entry is
> core-avx2, which should be based on new architecture. I propose
> PROCESSOR_HASWELL, in the same way as we have PROCESSOR_NOCONA.
>
> Uros.
>
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 08e1afe..2d8abd5 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -142,11 +142,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__corei7");
def_or_undef (parse_in, "__corei7__");
break;
- case PROCESSOR_CORE_AVX:
- def_or_undef (parse_in, "__core_avx");
- def_or_undef (parse_in, "__core_avx__");
- break;
- case PROCESSOR_CORE_AVX2:
+ case PROCESSOR_HASWELL:
def_or_undef (parse_in, "__core_avx2");
def_or_undef (parse_in, "__core_avx2__");
break;
@@ -240,10 +236,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_COREI7:
def_or_undef (parse_in, "__tune_corei7__");
break;
- case PROCESSOR_CORE_AVX:
- def_or_undef (parse_in, "__tune_core_avx__");
- break;
- case PROCESSOR_CORE_AVX2:
+ case PROCESSOR_HASWELL:
def_or_undef (parse_in, "__tune_core_avx2__");
break;
case PROCESSOR_ATOM:
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 10411da..4adbef6 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1732,9 +1732,8 @@ const struct processor_costs *ix86_cost = &pentium_cost;
#define m_P4_NOCONA (m_PENT4 | m_NOCONA)
#define m_CORE2 (1<<PROCESSOR_CORE2)
#define m_COREI7 (1<<PROCESSOR_COREI7)
-#define m_CORE_AVX (1<<PROCESSOR_CORE_AVX)
-#define m_CORE_AVX2 (1<<PROCESSOR_CORE_AVX2)
-#define m_CORE_ALL (m_CORE2 | m_COREI7 | m_CORE_AVX | m_CORE_AVX2)
+#define m_HASWELL (1<<PROCESSOR_HASWELL)
+#define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
#define m_ATOM (1<<PROCESSOR_ATOM)
#define m_GEODE (1<<PROCESSOR_GEODE)
@@ -2438,8 +2437,6 @@ static const struct ptt
processor_target_table[PROCESSOR_max] =
{&core_cost, 16, 10, 16, 10, 16},
/* Core i7 */
{&core_cost, 16, 10, 16, 10, 16},
- /* Core avx */
- {&core_cost, 16, 10, 16, 10, 16},
/* Core avx2 */
{&core_cost, 16, 10, 16, 10, 16},
{&generic32_cost, 16, 7, 16, 7, 16},
@@ -2469,7 +2466,6 @@ static const char *const
cpu_names[TARGET_CPU_DEFAULT_max] =
"nocona",
"core2",
"corei7",
- "coreavx",
"coreavx2",
"atom",
"geode",
@@ -2912,17 +2908,17 @@ ix86_option_override_internal (bool main_args_p)
{"corei7", PROCESSOR_COREI7, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_FXSR},
- {"corei7-avx", PROCESSOR_CORE_AVX, CPU_COREI7,
+ {"corei7-avx", PROCESSOR_COREI7, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
- {"core-avx-i", PROCESSOR_CORE_AVX, CPU_COREI7,
+ {"core-avx-i", PROCESSOR_COREI7, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
| PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
- {"core-avx2", PROCESSOR_CORE_AVX2, CPU_COREI7,
+ {"core-avx2", PROCESSOR_HASWELL, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
@@ -24069,8 +24065,7 @@ ix86_issue_rate (void)
case PROCESSOR_PENTIUM4:
case PROCESSOR_CORE2:
case PROCESSOR_COREI7:
- case PROCESSOR_CORE_AVX:
- case PROCESSOR_CORE_AVX2:
+ case PROCESSOR_HASWELL:
case PROCESSOR_ATHLON:
case PROCESSOR_K8:
case PROCESSOR_AMDFAM10:
@@ -24327,8 +24322,7 @@ ia32_multipass_dfa_lookahead (void)
case PROCESSOR_CORE2:
case PROCESSOR_COREI7:
- case PROCESSOR_CORE_AVX:
- case PROCESSOR_CORE_AVX2:
+ case PROCESSOR_HASWELL:
case PROCESSOR_ATOM:
/* Generally, we want haifa-sched:max_issue() to look ahead as far
as many instructions can be executed on a cycle, i.e.,
@@ -24873,8 +24867,7 @@ ix86_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
{
case PROCESSOR_CORE2:
case PROCESSOR_COREI7:
- case PROCESSOR_CORE_AVX:
- case PROCESSOR_CORE_AVX2:
+ case PROCESSOR_HASWELL:
/* Do not perform multipass scheduling for pre-reload schedule
to save compile time. */
if (reload_completed)
@@ -28719,11 +28712,7 @@ get_builtin_code_for_version (tree decl, tree
*predicate_list)
arg_str = "corei7";
priority = P_PROC_SSE4_2;
break;
- case PROCESSOR_CORE_AVX:
- arg_str = "core_avx";
- priority = P_PROC_SSE4_2;
- break;
- case PROCESSOR_CORE_AVX2:
+ case PROCESSOR_HASWELL:
arg_str = "core_avx2";
priority = P_PROC_SSE4_2;
break;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index d3ee8b0..ee21c47 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -248,8 +248,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
#define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7)
-#define TARGET_CORE_AVX (ix86_tune == PROCESSOR_CORE_AVX)
-#define TARGET_CORE_AVX2 (ix86_tune == PROCESSOR_CORE_AVX2)
+#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
@@ -605,8 +604,7 @@ enum target_cpu_default
TARGET_CPU_DEFAULT_nocona,
TARGET_CPU_DEFAULT_core2,
TARGET_CPU_DEFAULT_corei7,
- TARGET_CPU_DEFAULT_core_avx,
- TARGET_CPU_DEFAULT_core_avx2,
+ TARGET_CPU_DEFAULT_haswell,
TARGET_CPU_DEFAULT_atom,
TARGET_CPU_DEFAULT_geode,
@@ -2099,8 +2097,7 @@ enum processor_type
PROCESSOR_NOCONA,
PROCESSOR_CORE2,
PROCESSOR_COREI7,
- PROCESSOR_CORE_AVX,
- PROCESSOR_CORE_AVX2,
+ PROCESSOR_HASWELL,
PROCESSOR_GENERIC32,
PROCESSOR_GENERIC64,
PROCESSOR_AMDFAM10,
