Index: gcc/config/mips/constraints.md =================================================================== --- gcc/config/mips/constraints.md (revision 196638) +++ gcc/config/mips/constraints.md (working copy) @@ -43,6 +43,9 @@ (define_register_constraint "b" "ALL_REGS" "@internal") +(define_register_constraint "u" "M16_REGS" + "@internal") + ;; MIPS16 code always calls through a MIPS16 register; see mips_emit_call_insn ;; for details. (define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS @@ -170,6 +173,59 @@ (and (match_operand 0 "call_insn_operand") (match_test "CONSTANT_P (op)"))) +(define_constraint "Udb07" + "@internal + A decremented unsigned constant of 7 bits." + (match_operand 0 "Udb07_operand" "")) + +(define_constraint "Ueand" + "@internal + A microMIPS encoded andi operand." + (match_operand 0 "Ueand_operand" "")) + +(define_constraint "Ueas6" + "@internal + A microMIPS encoded ADDIUR1SP operand." + (match_operand 0 "Ueas6_operand" "")) + +(define_constraint "Ueas9" + "@internal + A microMIPS encoded ADDIUSP operand." + (match_operand 0 "Ueas9_operand" "")) + +(define_constraint "Ueim4" + "@internal + A microMIPS encoded ADDIUR2 immediate operand." + (match_operand 0 "Ueim4_operand" "")) + +(define_memory_constraint "Umem0" + "@internal + A microMIPS memory operand for use with the LWSP/SWSP insns." + (and (match_code "mem") + (match_operand 0 "Umem0_operand" ""))) + +(define_memory_constraint "Uload" + "@internal + A microMIPS memory operand for use with the various LOAD insns." + (and (match_code "mem") + (match_operand 0 "Uload_operand" ""))) + +(define_memory_constraint "Ustor" + "@internal + A microMIPS memory operand for use with the various STORE insns." + (and (match_code "mem") + (match_operand 0 "Ustore_operand" ""))) + +(define_constraint "Usb03" + "@internal + A signed three-bit constant." + (match_operand 0 "Usb03_operand" "")) + +(define_constraint "Uib03" + "@internal + An unsigned, incremented three-bit constant." + (match_operand 0 "Uib03_operand" "")) + (define_memory_constraint "W" "@internal A memory address based on a member of @code{BASE_REG_CLASS}. This is Index: gcc/config/mips/predicates.md =================================================================== --- gcc/config/mips/predicates.md (revision 196638) +++ gcc/config/mips/predicates.md (working copy) @@ -122,6 +122,61 @@ ? M16_REG_P (REGNO (op)) : GP_REG_P (REGNO (op))"))) +(define_predicate "Umem0_operand" + (and (match_code "mem") + (match_test "umips_lwsp_swsp_address_p (XEXP (op, 0), mode)"))) + +(define_predicate "Uload_operand" + (and (match_code "mem") + (match_test "umips_address_p (XEXP (op, 0), true, mode)"))) + +(define_predicate "Ustore_operand" + (and (match_code "mem") + (match_test "umips_address_p (XEXP (op, 0), false, mode)"))) + +(define_predicate "Udb07_operand" + (and (match_code "const_int") + (match_test "mips_unsigned_immediate_p (INTVAL (op) + 1, 7, 0)"))) + +(define_predicate "Ueas9_operand" + (and (match_code "const_int") + (ior (match_test "(IN_RANGE (INTVAL (op), 2, 257))") + (match_test "(IN_RANGE (INTVAL (op), -258, -3))")))) + +(define_predicate "Ueas6_operand" + (and (match_code "const_int") + (match_test "mips_unsigned_immediate_p (INTVAL (op), 8, 2)"))) + +(define_predicate "Ueim4_operand" + (and (match_code "const_int") + (ior (match_test "INTVAL (op) == -1") + (match_test "INTVAL (op) == 1") + (match_test "INTVAL (op) == 4") + (match_test "INTVAL (op) == 8") + (match_test "INTVAL (op) == 12") + (match_test "INTVAL (op) == 16") + (match_test "INTVAL (op) == 20") + (match_test "INTVAL (op) == 24")))) + +(define_predicate "Ueand_operand" + (and (match_code "const_int") + (ior (match_test "IN_RANGE (INTVAL (op), 1, 4)") + (match_test "IN_RANGE (INTVAL (op), 7, 8)") + (match_test "IN_RANGE (INTVAL (op), 15, 16)") + (match_test "IN_RANGE (INTVAL (op), 31, 32)") + (match_test "IN_RANGE (INTVAL (op), 63, 64)") + (match_test "INTVAL (op) == 255") + (match_test "INTVAL (op) == 32768") + (match_test "INTVAL (op) == 65535")))) + +(define_predicate "Usb03_operand" + (and (match_code "const_int") + (match_test "mips_signed_immediate_p (INTVAL (op), 3, 0)"))) + +(define_predicate "Uib03_operand" + (and (match_code "const_int") + (match_test "mips_unsigned_immediate_p (INTVAL (op) - 1, 3, 0)"))) + (define_predicate "movep_src_register" (and (match_code "reg") (ior (match_test ("IN_RANGE (REGNO (op), 2, 3)")) Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md (revision 196638) +++ gcc/config/mips/mips.md (working copy) @@ -412,12 +412,29 @@ (const_string "yes") (const_string "no"))) +(define_attr "compression" "none,all,micromips,mips16" + (const_string "none")) + +(define_attr "enabled" "no,yes" + (if_then_else (ior (eq_attr "compression" "all") + (eq_attr "compression" "none") + (and (eq_attr "compression" "micromips") + (match_test "TARGET_MICROMIPS"))) + (const_string "yes") + (const_string "no"))) + ;; Length of instruction in bytes. (define_attr "length" "" (cond [(and (eq_attr "extended_mips16" "yes") (match_test "TARGET_MIPS16")) (const_int 8) + (and (ior (eq_attr "compression" "micromips") + (eq_attr "compression" "all")) + (eq_attr "dword_mode" "no") + (match_test "TARGET_MICROMIPS")) + (const_int 2) + ;; Direct microMIPS branch instructions have a range of ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc]. ;; If a branch is outside this range, we have a choice of two @@ -1131,14 +1148,19 @@ "") (define_insn "*add3" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (plus:GPR (match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "arith_operand" "d,Q")))] + [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!ks,d,d,d") + (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,0,!ks,!ks,d") + (match_operand:GPR 2 "arith_operand" "!u,d,Ueim4,Usb03,Ueas9,Ueas6,Q")))] "!TARGET_MIPS16" - "@ - addu\t%0,%1,%2 - addiu\t%0,%1,%2" +{ + if (which_alternative == 0 + || which_alternative == 1) + return "addu\t%0,%1,%2"; + else + return "addiu\t%0,%1,%2"; +} [(set_attr "alu_type" "add") + (set_attr "compression" "micromips,*,micromips,micromips,micromips,micromips,*") (set_attr "mode" "")]) (define_insn "*add3_mips16" @@ -1347,12 +1369,13 @@ (set_attr "mode" "")]) (define_insn "sub3" - [(set (match_operand:GPR 0 "register_operand" "=d") - (minus:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d")))] + [(set (match_operand:GPR 0 "register_operand" "=!u,d") + (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d") + (match_operand:GPR 2 "register_operand" "!u,d")))] "" - "subu\t%0,%1,%2" +{ return "subu\t%0,%1,%2"; } [(set_attr "alu_type" "sub") + (set_attr "compression" "micromips,*") (set_attr "mode" "")]) (define_insn "*subsi3_extended" @@ -2828,8 +2851,8 @@ (set_attr "mode" "")]) (define_insn "one_cmpl2" - [(set (match_operand:GPR 0 "register_operand" "=d") - (not:GPR (match_operand:GPR 1 "register_operand" "d")))] + [(set (match_operand:GPR 0 "register_operand" "=!u,d") + (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))] "" { if (TARGET_MIPS16) @@ -2838,6 +2861,7 @@ return "nor\t%0,%.,%1"; } [(set_attr "alu_type" "not") + (set_attr "compression" "micromips,*") (set_attr "mode" "")]) ;; @@ -2878,9 +2902,9 @@ ;; register =op1 x (define_insn "*and3" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d") - (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,d,d,d,d") - (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,K,Yx,Yw,d")))] + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d") + (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d") + (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Ueand,K,Yx,Yw,!u,d")))] "!TARGET_MIPS16 && and_operands_ok (mode, operands[1], operands[2])" { int len; @@ -2897,20 +2921,23 @@ operands[1] = gen_lowpart (SImode, operands[1]); return "lwu\t%0,%1"; case 3: + case 4: return "andi\t%0,%1,%x2"; - case 4: + case 5: len = low_bitmask_len (mode, INTVAL (operands[2])); operands[2] = GEN_INT (len); return "ext\t%0,%1,0,%2"; - case 5: + case 6: return "#"; - case 6: + case 7: + case 8: return "and\t%0,%1,%2"; default: gcc_unreachable (); } } - [(set_attr "move_type" "load,load,load,andi,ext_ins,shift_shift,logical") + [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical") + (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*") (set_attr "mode" "")]) (define_insn "*and3_mips16" @@ -2952,14 +2979,16 @@ }) (define_insn "*ior3" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d") - (match_operand:GPR 2 "uns_arith_operand" "d,K")))] + [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") + (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") + (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))] "!TARGET_MIPS16" "@ or\t%0,%1,%2 + or\t%0,%1,%2 ori\t%0,%1,%x2" [(set_attr "alu_type" "or") + (set_attr "compression" "micromips,*,*") (set_attr "mode" "")]) (define_insn "*ior3_mips16" @@ -2979,14 +3008,16 @@ "") (define_insn "" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d") - (match_operand:GPR 2 "uns_arith_operand" "d,K")))] + [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") + (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") + (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))] "!TARGET_MIPS16" "@ xor\t%0,%1,%2 + xor\t%0,%1,%2 xori\t%0,%1,%x2" [(set_attr "alu_type" "xor") + (set_attr "compression" "micromips,*,*") (set_attr "mode" "")]) (define_insn "" @@ -3162,14 +3193,16 @@ }) (define_insn "*zero_extend2" - [(set (match_operand:GPR 0 "register_operand" "=d,d") + [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") (zero_extend:GPR - (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] + (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))] "!TARGET_MIPS16" "@ andi\t%0,%1, + andi\t%0,%1, lu\t%0,%1" - [(set_attr "move_type" "andi,load") + [(set_attr "move_type" "andi,andi,load") + (set_attr "compression" "micromips,*,*") (set_attr "mode" "")]) (define_insn "*zero_extend2_mips16e" @@ -4362,13 +4395,14 @@ ;; in FP registers (off by default, use -mdebugh to enable). (define_insn "*mov_internal" - [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") - (match_operand:IMOVE32 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] + [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,d,e,!u,!u,d,d,Umem0,Ustor,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") + (match_operand:IMOVE32 1 "move_operand" "d,J,Yd,Yf,Udb07,Uload,Umem0,m,ks,!u,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "!TARGET_MIPS16 && (register_operand (operands[0], mode) || reg_or_0_operand (operands[1], mode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore") + [(set_attr "move_type" "move,move,const,const,load,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore") + (set_attr "compression" "all,micromips,*,*,micromips,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*") (set_attr "mode" "SI")]) (define_insn "*mov_mips16" @@ -5225,9 +5259,9 @@ }) (define_insn "*3" - [(set (match_operand:GPR 0 "register_operand" "=d") - (any_shift:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:SI 2 "arith_operand" "dI")))] + [(set (match_operand:GPR 0 "register_operand" "=!u,d") + (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d") + (match_operand:SI 2 "arith_operand" "Uib03,dI")))] "!TARGET_MIPS16" { if (CONST_INT_P (operands[2])) @@ -5237,6 +5271,12 @@ return "\t%0,%1,%2"; } [(set_attr "type" "shift") + (set_attr_alternative "compression" + [(if_then_else (ior (match_test "GET_CODE (SET_SRC (PATTERN (insn))) == ASHIFT") + (match_test "GET_CODE (SET_SRC (PATTERN (insn))) == LSHIFTRT")) + (const_string "micromips") + (const_string "none")) + (const_string "none")]) (set_attr "mode" "")]) (define_insn "*si3_extend" Index: gcc/config/mips/mips-protos.h =================================================================== --- gcc/config/mips/mips-protos.h (revision 196638) +++ gcc/config/mips/mips-protos.h (working copy) @@ -350,12 +350,19 @@ extern void mips_expand_vec_reduc (rtx, rtx, rtx ( extern void mips_expand_vec_minmax (rtx, rtx, rtx, rtx (*) (rtx, rtx, rtx), bool); +extern bool mips_signed_immediate_p (unsigned HOST_WIDE_INT, int, int); +extern bool mips_unsigned_immediate_p (unsigned HOST_WIDE_INT, int, int); + extern const char *umips_output_save_restore (bool, rtx); extern bool umips_save_restore_pattern_p (bool, rtx); extern bool umips_load_store_pair_p (bool, rtx *); extern void umips_output_load_store_pair (bool, rtx *); extern bool umips_movep_target_p (rtx, rtx); + +extern bool umips_lwsp_swsp_address_p (rtx, enum machine_mode); +extern bool umips_address_p (rtx, bool, enum machine_mode); extern bool umips_12bit_offset_address_p (rtx, enum machine_mode); + extern rtx mips_expand_thread_pointer (rtx); extern bool mips_eh_uses (unsigned int); Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c (revision 196638) +++ gcc/config/mips/mips.c (working copy) @@ -2377,6 +2377,71 @@ mips_address_insns (rtx x, enum machine_mode mode, return 0; } +/* Return true if X fits within an unsigned field of BITS bits that is + shifted left SHIFT bits before being used. */ + +bool +mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0) +{ + return (x & ((1 << shift) - 1)) == 0 && x < (1 << (shift + bits)); +} + +/* Return true if X fits within a signed field of BITS bits that is + shifted left SHIFT bits before being used. */ + +bool +mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0) +{ + x += 1 << (bits + shift - 1); + return mips_unsigned_immediate_p (x, bits, shift); +} + +/* Return true if X is a legitimate address that conforms to the requirements + for any of the short microMIPS LOAD or STORE instructions except LWSP + or SWSP. */ + +bool +umips_address_p (rtx x, bool load, enum machine_mode mode) +{ + + struct mips_address_info addr; + bool ok = mips_classify_address (&addr, x, mode, false) + && addr.type == ADDRESS_REG + && M16_REG_P (REGNO (addr.reg)) + && CONST_INT_P (addr.offset); + + if (!ok) + return false; + + if (mips_unsigned_immediate_p (INTVAL (addr.offset), 4, 2) + || mips_unsigned_immediate_p (INTVAL (addr.offset), 4, 1)) + return true; + + if (load && IN_RANGE (INTVAL (addr.offset), -1, 14)) + return true; + + if (!load && IN_RANGE (INTVAL (addr.offset), 0, 15)) + return true; + + return false; + +} + +/* Return true if X is a legitimate address that conforms to the requirements + for a microMIPS LWSP or SWSP insn. */ + +bool +umips_lwsp_swsp_address_p (rtx x, enum machine_mode mode) +{ + struct mips_address_info addr; + + return (mips_classify_address (&addr, x, mode, false) + && addr.type == ADDRESS_REG + && REGNO (addr.reg) == STACK_POINTER_REGNUM + && CONST_INT_P (addr.offset) + && mips_unsigned_immediate_p (INTVAL (addr.offset), 5, 2)); +} + /* Return true if X is a legitimate address with a 12-bit offset. MODE is the mode of the value being accessed. */ @@ -8010,9 +8075,17 @@ mips_print_operand_punctuation (FILE *file, int ch case '!': /* When final_sequence is 0, the delay slot will be a nop. We can - a 16-bit delay slot for microMIPS. */ + use a 16-bit delay slot for microMIPS. */ if (final_sequence == 0) putc ('s', file); + else + { + /* Use the compact version for microMIPS if the delay slot is a + compact microMIPS instruction. */ + rtx insn = XVECEXP (final_sequence, 0, 1); + if (get_attr_length (insn) == 2) + putc ('s', file); + } break; default: