diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5370efa..8611023 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -8754,7 +8754,7 @@ (define_expand "movsfcc" [(set (match_operand:SF 0 "s_register_operand" "") - (if_then_else:SF (match_operand 1 "expandable_comparison_operator" "") + (if_then_else:SF (match_operand 1 "arm_cond_move_operator" "") (match_operand:SF 2 "s_register_operand" "") (match_operand:SF 3 "s_register_operand" "")))] "TARGET_32BIT && TARGET_HARD_FLOAT" @@ -8776,7 +8776,7 @@ (define_expand "movdfcc" [(set (match_operand:DF 0 "s_register_operand" "") - (if_then_else:DF (match_operand 1 "expandable_comparison_operator" "") + (if_then_else:DF (match_operand 1 "arm_cond_move_operator" "") (match_operand:DF 2 "s_register_operand" "") (match_operand:DF 3 "s_register_operand" "")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 3cec569..179fec8 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -316,6 +316,12 @@ || maybe_get_arm_condition_code (op) == ARM_NE || maybe_get_arm_condition_code (op) == ARM_VC"))) +(define_special_predicate "arm_cond_move_operator" + (if_then_else (match_test "arm_restrict_it") + (and (match_test "TARGET_FPU_ARMV8") + (match_operand 0 "arm_vsel_comparison_operator")) + (match_operand 0 "expandable_comparison_operator"))) + (define_special_predicate "noov_comparison_operator" (match_code "lt,ge,eq,ne")) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 1930cdd..10e193c 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -412,6 +412,7 @@ } " [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") @@ -420,7 +421,6 @@ (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] ) - ;; DFmode moves (define_insn "*movdf_vfp" @@ -550,7 +550,7 @@ [(match_operand 4 "cc_register" "") (const_int 0)]) (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t") (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" + "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it" "@ it\\t%D3\;fcpys%D3\\t%0, %2 it\\t%d3\;fcpys%d3\\t%0, %1 @@ -598,7 +598,7 @@ [(match_operand 4 "cc_register" "") (const_int 0)]) (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it" "@ it\\t%D3\;fcpyd%D3\\t%P0, %P2 it\\t%d3\;fcpyd%d3\\t%P0, %P1 @@ -624,6 +624,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fabss%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "ffariths")] ) @@ -633,6 +634,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fabsd%?\\t%P0, %P1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "ffarithd")] ) @@ -644,6 +646,7 @@ fnegs%?\\t%0, %1 eor%?\\t%0, %1, #-2147483648" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "ffariths")] ) @@ -689,6 +692,7 @@ } " [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "length" "4,4,8") (set_attr "type" "ffarithd")] ) @@ -703,6 +707,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fadds%?\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fadds")] ) @@ -713,6 +718,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "faddd%?\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "faddd")] ) @@ -724,6 +730,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fsubs%?\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fadds")] ) @@ -734,6 +741,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fsubd%?\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "faddd")] ) @@ -747,6 +755,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fdivs%?\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fdivs")] ) @@ -757,6 +766,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fdivd%?\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fdivd")] ) @@ -770,6 +780,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fmuls%?\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmuls")] ) @@ -780,6 +791,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fmuld%?\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmuld")] ) @@ -790,6 +802,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fnmuls%?\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmuls")] ) @@ -800,6 +813,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fnmuld%?\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmuld")] ) @@ -815,6 +829,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fmacs%?\\t%0, %2, %3" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] ) @@ -826,6 +841,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fmacd%?\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] ) @@ -838,6 +854,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fmscs%?\\t%0, %2, %3" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] ) @@ -849,6 +866,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fmscd%?\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] ) @@ -861,6 +879,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fnmacs%?\\t%0, %2, %3" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] ) @@ -872,6 +891,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fnmacd%?\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] ) @@ -886,6 +906,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fnmscs%?\\t%0, %2, %3" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] ) @@ -898,6 +919,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fnmscd%?\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] ) @@ -911,6 +933,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" "vfma%?.\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "ffma")] ) @@ -923,6 +946,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" "vfms%?.\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "ffma")] ) @@ -934,6 +958,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" "vfnms%?.\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "ffma")] ) @@ -946,6 +971,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" "vfnma%?.\\t%0, %1, %2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "ffma")] ) @@ -958,6 +984,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fcvtds%?\\t%P0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -967,6 +994,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fcvtsd%?\\t%0, %P1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -976,6 +1004,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16" "vcvtb%?.f32.f16\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -985,6 +1014,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16" "vcvtb%?.f16.f32\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -994,6 +1024,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "ftosizs%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1003,6 +1034,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "ftosizd%?\\t%0, %P1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1013,6 +1045,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "ftouizs%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1022,6 +1055,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "ftouizd%?\\t%0, %P1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1032,6 +1066,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fsitos%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1041,6 +1076,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fsitod%?\\t%P0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1051,6 +1087,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fuitos%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1060,6 +1097,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fuitod%?\\t%P0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1072,6 +1110,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "fsqrts%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fdivs")] ) @@ -1081,6 +1120,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "fsqrtd%?\\t%P0, %P1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fdivd")] ) @@ -1168,6 +1208,7 @@ fcmps%?\\t%0, %1 fcmpzs%?\\t%0" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fcmps")] ) @@ -1180,6 +1221,7 @@ fcmpes%?\\t%0, %1 fcmpezs%?\\t%0" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fcmps")] ) @@ -1192,6 +1234,7 @@ fcmpd%?\\t%P0, %P1 fcmpzd%?\\t%P0" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fcmpd")] ) @@ -1204,6 +1247,7 @@ fcmped%?\\t%P0, %P1 fcmpezd%?\\t%P0" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "fcmpd")] ) @@ -1263,6 +1307,7 @@ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vrint%?.\\t%0, %1" [(set_attr "predicable" "") + (set_attr "predicable_short_it" "no") (set_attr "type" "f_rint")] )