Mike, This patch is okay, but something seems really broken with respect to TImode. I don't know if we have to separate TImode from V1TImode or some distinction for atomics from other uses of TImode. This isn't like float modes where they mostly live in FPRs and only occassionally need to live in GPRs. TImode between VSX and GPRs really is bimodal. Something is wrong with this preferencing design.
Maybe we need a separate set of logical TImode instructions for the atomic ops with a neutral set of preferences on the constraints for movti. Then the registers chosen for the computation will correctly drive the register allocation decisions. Thanks, David
