On 01/08/13 14:02, Kyrylo Tkachov wrote:
+;; Rd = (eq (reg1) (reg2/imm)) // optimize for size on Thumb2
+;; subs T1, Reg1, reg2
+;; negs Rd, T1
+;; adcs Rd, Rd, T1
Only the second operation has to be flag setting. A later pass will
convert the first and third instructions to flag clobbering if that's
the right thing to do on the target (which it currently always is, but
may not always remain so).
So I tried removing the flag setting from the peephole for the sub and
adc
instructions, and nothing ends up converting them to flag-setting
instructions
and we end up with:
sub
negs
adc
which is suboptimal for size. Is combine supposed to do decide whether
to use
flag-setting variants?
thumb2_reorg should be picking both up. It already has code for sub,
but currently doesn't handle adc. You need to investigate the former
and perhaps write some code for the latter.
Thanks, that's where the culprit turned out to be.
Turns out the peephole generated the non-canonical subtract-immediate form
that was not getting matched in thumb2_reorg. So fixing the peephole got the
235.mach pass to emit the flag-setting variant correctly.
Also, I've added some matching for the add-with-carry case in thumb2_reorg so
that the flag-setting variant of ADC is used. Now for the testcase, when
optimising for size we get only 3 16-bit instructions.
Tested arm-none-eabi on qemu with and without -mthumb.
Ok?
Thanks,
Kyrill
2013-08-01 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/arm.md (peepholes for eq (reg1) (reg2/imm)):
Generate canonical plus rtx with negated immediate instead of minus
where
appropriate.
* config/arm/arm.c (thumb2_reorg): Handle ADCS <Rd>, <Rn> case.
2013-08-01 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* gcc.target/arm/pr46972-2.c: New test.
OK.
R.
