This fixes PR58460, the add and sub shifted register instruction forms
in AArch64 do not permit the stack register. This patch removes k
constraint from the relevant patterns and adds reduced form of the test
case.
Regression test aarch64-none-elf. Committed.
/Marcus
2013-10-03 Marcus Shawcroft <marcus.shawcr...@arm.com>
PR target/58460
* config/aarch64/aarch64.md (*adds_mul_imm_<mode>)
(*subs_mul_imm_<mode>)
(*add_<shift>_<mode>, *add_<shift>_si_uxtw,*add_mul_imm_<mode>)
(*sub_<shift>_<mode>)
(*sub_<shift>_si_uxtw,*sub_mul_imm_<mode>, *sub_mul_imm_si_uxtw):
Remove k constraint.
2013-10-03 Marcus Shawcroft <marcus.shawcr...@arm.com>
PR target/58460
* gcc.target/aarch64/pr58460.c: New file.diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 830bbee..f3e004b 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1365,7 +1365,7 @@
(plus:GPI (mult:GPI
(match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
- (match_operand:GPI 3 "register_operand" "rk"))
+ (match_operand:GPI 3 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
@@ -1380,7 +1380,7 @@
(define_insn "*subs_mul_imm_<mode>"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
- (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
+ (minus:GPI (match_operand:GPI 1 "register_operand" "r")
(mult:GPI
(match_operand:GPI 2 "register_operand" "r")
(match_operand:QI 3 "aarch64_pwr_2_<mode>" "n")))
@@ -1500,7 +1500,7 @@
)
(define_insn "*add_<shift>_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_<mode>"
"n"))
(match_operand:GPI 3 "register_operand" "r")))]
@@ -1513,7 +1513,7 @@
;; zero_extend version of above
(define_insn "*add_<shift>_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(plus:SI (ASHIFT:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_si" "n"))
@@ -1526,7 +1526,7 @@
)
(define_insn "*add_mul_imm_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
(match_operand:GPI 3 "register_operand" "r")))]
@@ -1873,7 +1873,7 @@
)
(define_insn "*sub_<shift>_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_operand:GPI 3 "register_operand" "r")
(ASHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -1887,7 +1887,7 @@
;; zero_extend version of above
(define_insn "*sub_<shift>_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 3 "register_operand" "r")
(ASHIFT:SI
@@ -1901,7 +1901,7 @@
)
(define_insn "*sub_mul_imm_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_operand:GPI 3 "register_operand" "r")
(mult:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -1915,7 +1915,7 @@
;; zero_extend version of above
(define_insn "*sub_mul_imm_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 3 "register_operand" "r")
(mult:SI
diff --git a/gcc/testsuite/gcc.target/aarch64/pr58460.c
b/gcc/testsuite/gcc.target/aarch64/pr58460.c
new file mode 100644
index 0000000..a7e149a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr58460.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+extern unsigned long x1;
+
+char *
+f (char *a, char *b)
+{
+ return a;
+}
+
+int
+g (char *a)
+{
+ return 2;
+}
+
+void
+h (char *p[])
+{
+ char n[x1][512];
+ char *l = f (p[1], " ");
+ if (g (p[0]))
+ n[0][0] = '\0';
+ while (l && *l)
+ {
+ }
+}
+
+unsigned long x1;
+
+int
+main ()
+{
+ return 0;
+}
