Hello!
> This patch adds the support to two non-isomorphic operations addsub
> and subadd for SLP vectorizer. More non-isomorphic operations can be
> added later, but the limitation is that operations on even/odd
> elements should still be isomorphic. Once such an operation is
> detected, the code of the operation used in vectorized code is stored
> and later will be used during statement transformation. Two new GIMPLE
> opeartions VEC_ADDSUB_EXPR and VEC_SUBADD_EXPR are defined. And also
> new optabs for them. They are also documented.
>
> The target supports for SSE/SSE2/SSE3/AVX are added for those two new
> operations on floating points. SSE3/AVX provides ADDSUBPD and ADDSUBPS
> instructions. For SSE/SSE2, those two operations are emulated using
> two instructions (selectively negate then add).
;; SSE3
UNSPEC_LDDQU
+ UNSPEC_SUBADD
+ UNSPEC_ADDSUB
No! Please avoid unspecs.
+(define_expand "vec_subadd_v4sf3"
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF
+ [(match_operand:V4SF 1 "register_operand")
+ (match_operand:V4SF 2 "nonimmediate_operand")] UNSPEC_SUBADD))]
+ "TARGET_SSE"
+{
+ if (TARGET_SSE3)
+ emit_insn (gen_sse3_addsubv4sf3 (operands[0], operands[1], operands[2]));
+ else
+ ix86_sse_expand_fp_addsub_operator (true, V4SFmode, operands);
+ DONE;
+})
Make the expander pattern look like correspondig sse3 insn and:
...
{
if (!TARGET_SSE3)
{
ix86_sse_expand_fp_...();
DONE;
}
}
Uros.
