On Thu, Nov 21, 2013 at 5:09 PM, Martin Jambor <mjam...@suse.cz> wrote: > Hi, > > the patch below enables IRA live-range splitting that later > facilitates shrink-wrapping also work on ppc64. The difference is > that while on x86_64 it was enough to look for single sets from a hard > register to a pseudo in the first BB, on ppc the instructions are more > complicated and can look like this (example from pr10474.c testcase): > > (insn 6 3 7 2 (parallel [ > (set (reg:CC 124) > (compare:CC (reg:DI 3 3 [ i ]) > (const_int 0 [0]))) > (set (reg/v/f:DI 123 [ i ]) > (reg:DI 3 3 [ i ])) > ]) pr10474.c:6 428 {*movdi_internal2} > (expr_list:REG_DEAD (reg:DI 3 3 [ i ]) > (nil)))
IIUC if this is the pattern you are detecting, this should help AArch32 in ARM state as well in the testcases you have attached particular case especially as this sort of rtl insn what we'd generate in this testcase (except ofcourse in SImode.) Is there any reason why these tests are so restricted to lp64 only targets ? ramana