Hi,
This patch back ported a trunk M4 CPU pipeline tuning to
embedded-4_8-branch.
BR,
Terry
gcc/ChangeLog.arm
2013-11-28 Terry Guo <terry....@arm.com>
Backport mainline r198021
2013-04-17 Terry Guo <terry....@arm.com>
* config/arm/cortex-m4.md: Add a new bypass.
The patch itself:
Index: gcc/config/arm/cortex-m4.md
===================================================================
--- gcc/config/arm/cortex-m4.md (revision 205472)
+++ gcc/config/arm/cortex-m4.md (working copy)
@@ -84,6 +84,10 @@
(eq_attr "type" "store4"))
"cortex_m4_ex*5")
+(define_bypass 1 "cortex_m4_load1"
+ "cortex_m4_store1_1,cortex_m4_store1_2"
+ "arm_no_early_store_addr_dep")
+
;; If the address of load or store depends on the result of the preceding
;; instruction, the latency is increased by one.
