On Mon, Dec 23, 2013 at 8:57 AM, Allan Sandfeld Jensen <carew...@gmail.com> wrote: > On Monday 23 December 2013, Allan Sandfeld Jensen wrote: >> On Monday 23 December 2013, H.J. Lu wrote: >> > On Thu, Dec 19, 2013 at 11:20:39AM +0100, Allan Sandfeld Jensen wrote: >> > > On Thursday 19 December 2013, Gopalasubramanian, Ganesh wrote: >> > > > > Sorry, I must have been looking at an older version, but as I said >> > > > > I already did enable it in the latest patch. (see >> > > > > http://gcc.gnu.org/ml/gcc-patches/2013-12/msg01577.html ) >> > > > >> > > > Sorry for causing another revision but we would like to stick with >> > > > "btver1" and "btver2" rather than "BOBCAT" or "JAGUAR". Therefore the >> > > > changes would be like >> > > >> > > I will need to make an updated patch to move the new ISAs to the end of >> > > the list anyway. I will send it in a few days to give AMD or Intel >> > > developers time to comment on the current version. >> > >> > I renamed Intel processor names. Please update your patch. Here is my >> > patch to add more Intel processor support. You can add it to your >> > patch. >> >> Updated patch attached. Rebased, fixed coding style, moved new ISA enums to >> the end and applied H.J.Lu's patch. >> > Fixed merging mistake that left haswell with SSE4_2 priority. > > `Allan
+ M_INTEL_COREI7_AVX, + M_INTEL_CORE_AVX2, Do we need them? M_INTEL_COREI7_AVX is the same M_INTEL_COREI7_SANDYBRIDGE and M_INTEL_CORE_AVX2 is the same as M_INTEL_COREI7_HASWELL. + M_INTEL_CORE_HASWELL Please change M_INTEL_CORE_HASWELL to M_INTEL_COREI7_HASWELL. + {"corei7-avx", M_INTEL_COREI7_AVX}, + {"core-avx2", M_INTEL_CORE_AVX2}, Why do we need them? -- H.J.