From c5c4550d136c8e3934bd6542f9b2912ef2eea516 Mon Sep 17 00:00:00 2001 From: David Holsgrove Date: Tue, 9 Jul 2013 20:40:15 +1000 Subject: [PATCH] [Patch, microblaze]: cstoresf4, add mode and ordered_comparison_operator Add SImode to comparison operator, prevents ICE during combine rtl pass with error message; internal compiler error: in simplify_subreg, at simplify-rtx.c:5725 Use ordered_comparison_operator predicate to limit operators to those fcmp can handle, and letting compiler reorder insns to accomodate unordered as necessary gcc/ChangeLog 2013-11-26 David Holsgrove * config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace comparison_operator with ordered_comparison_operator. testsuite/ChangeLog 2014-01-22 David holsgrove * testsuite/gcc.target/microblaze/isa/fcmp4.c: New file. Signed-off-by: David Holsgrove --- gcc/config/microblaze/microblaze.md | 4 ++-- gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 9 +++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 4b0ca1a..c1a1daa 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1649,7 +1649,7 @@ ;;---------------------------------------------------------------- (define_insn "cstoresf4" [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator 1 "comparison_operator" + (match_operator:SI 1 "ordered_comparison_operator" [(match_operand:SF 2 "register_operand" "r") (match_operand:SF 3 "register_operand" "r")]))] "TARGET_HARD_FLOAT" @@ -1678,7 +1678,7 @@ (define_expand "cbranchsf4" [(set (pc) - (if_then_else (match_operator 0 "comparison_operator" + (if_then_else (match_operator 0 "ordered_comparison_operator" [(match_operand:SF 1 "register_operand") (match_operand:SF 2 "register_operand")]) (label_ref (match_operand 3 "")) diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c new file mode 100644 index 0000000..79cc5f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c @@ -0,0 +1,9 @@ +/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */ + +void float_func(float f1, float f2, float f3) +{ + /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if(f1==f2 && f1<=f3) + print ("f1 eq f2 && f1 le f3"); +} -- 1.7.9.5