On 28 February 2014 10:30, Alex Velenko <alex.vele...@arm.com> wrote:
> Hi Richard, > Thank you for your suggestion. Attached is a patch that includes > implementation of your proposition. A testsuite was run on LE and BE > compilers with no regressions. > > Here is the description of the patch: > > This patch introduces vreinterpret implementation for vectors with 64-bit > float lanes and adds testcase for those intrinsics. The aarch64_init_simd_builtins() infrastructure requires the presence of named RTL patterns in order to construct the types of the SIMD intrinsics even when an intrinsic is emitted as tree. This seems rather ugly to me. At some point we should figure out how to clean up this aspect of aarch64_init_simd_builtins() and remove the otherwise unused .md patterns. This aside I think your patch is fine as it stands and can be committed in stage-1. Cheers /Marcus
