> I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI > (and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0xffffffff])) 4) to zero > during the fwprop1 pass, considering the fact that the high 32-bit part of > (a & 0xFFFFFFFF) is zero. This leads to some unnecessary multiplications > for high 32-bit part of the result of AND operation. The attached patch is > trying to improve simplify_rtx to handle such case. Other target like x86 > seems hasn't such issue because it generates different RTX to handle 64bit > multiplication on a 32bit machine.
See http://gcc.gnu.org/ml/gcc-patches/2013-05/msg00073.html for another try, which led to the simplification in combine.c:combine_simplify_rtx line 5448. Your variant is both more general, because it isn't restricted to the lowpart, and less general, because it is artificially restricted to AND. Some remarks: - this needs to be restricted to non-paradoxical subregs, - you need to test HWI_COMPUTABLE_MODE_P (innermode), - you need to test !side_effects_p (op). I think we need to find a common ground between Jakub's patch and yours and put a single transformation in simplify_subreg. -- Eric Botcazou
