Hi, This patch (diff-pr60735) adds to the 4.8 PowerPC backport patch series with a backported fix for PR60735, an unrecognized insn problem for SPE.
Thanks, Bill [gcc] 2014-04-03 Bill Schmidt <wschm...@linux.vnet.ibm.com> Back port mainline subversion id 209025. 2014-04-02 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/60735 * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have software floating point or no floating point registers, do not allow any type in the FPRs. Eliminate a test for SPE SIMD types in GPRs that occurs after we tested for GPRs that would never be true. * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64): Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, specifically allow DDmode, since that does not use the SPE SIMD instructions. Index: gcc-4_8-test2/gcc/config/rs6000/rs6000.c =================================================================== --- gcc-4_8-test2.orig/gcc/config/rs6000/rs6000.c +++ gcc-4_8-test2/gcc/config/rs6000/rs6000.c @@ -1733,6 +1733,9 @@ rs6000_hard_regno_mode_ok (int regno, en modes and DImode. */ if (FP_REGNO_P (regno)) { + if (TARGET_SOFT_FLOAT || !TARGET_FPRS) + return 0; + if (SCALAR_FLOAT_MODE_P (mode) && (mode != TDmode || (regno % 2) == 0) && FP_REGNO_P (last_regno)) @@ -1761,10 +1764,6 @@ rs6000_hard_regno_mode_ok (int regno, en return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) || mode == V1TImode); - /* ...but GPRs can hold SIMD data on the SPE in one register. */ - if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) - return 1; - /* We cannot put non-VSX TImode or PTImode anywhere except general register and it must be able to fit within the register set. */ Index: gcc-4_8-test2/gcc/config/rs6000/rs6000.md =================================================================== --- gcc-4_8-test2.orig/gcc/config/rs6000/rs6000.md +++ gcc-4_8-test2/gcc/config/rs6000/rs6000.md @@ -9428,8 +9428,9 @@ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r") (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] "! TARGET_POWERPC64 - && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) - || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) + && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) + || TARGET_SOFT_FLOAT + || (<MODE>mode == DDmode && TARGET_E500_DOUBLE)) && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" "#"