> On Apr 22, 2014, at 2:36 AM, Zhenqiang Chen <zhenqiang.c...@linaro.org> wrote:
>
> Ping?
>
> Rebase and test. Bootstrap and no make check regression with qemu.
>
> OK for trunk?
This is the exact same patch we (Cavium) came up with for this missed
optimization.
Thanks,
Andrew
>
> Thanks!
> -Zhenqiang
>
>> On 18 March 2014 16:16, Zhenqiang Chen <zhenqiang.c...@linaro.org> wrote:
>> Hi,
>>
>> For float value, movsfcc/movdfcc is required by emit_conditional_move
>> called in ifcvt pass to expand if-then-else to "fcsel" insn.
>>
>> Bootstrap and no make check regression with qemu-aarch64.
>>
>> Is it OK for next stage1?
>>
>> Thanks!
>> -Zhenqiang
>>
>> ChangeLog:
>> 2014-03-18 Zhenqiang Chen <zhenqiang.c...@linaro.org>
>>
>> * config/aarch64/aarch64.md (mov<mode>cc): New for GPF.
>>
>> testsuite/ChangeLog:
>> 2014-03-18 Zhenqiang Chen <zhenqiang.c...@linaro.org>
>>
>> * gcc.target/aarch64/fcsel.c: New test case.
>>
>> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
>> index 99a6ac8..0f4b8ebf 100644
>> --- a/gcc/config/aarch64/aarch64.md
>> +++ b/gcc/config/aarch64/aarch64.md
>> @@ -2344,6 +2344,25 @@
>> }
>> )
>>
>> +(define_expand "mov<mode>cc"
>> + [(set (match_operand:GPF 0 "register_operand" "")
>> + (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
>> + (match_operand:GPF 2 "register_operand" "")
>> + (match_operand:GPF 3 "register_operand" "")))]
>> + ""
>> + {
>> + rtx ccreg;
>> + enum rtx_code code = GET_CODE (operands[1]);
>> +
>> + if (code == UNEQ || code == LTGT)
>> + FAIL;
>> +
>> + ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
>> + XEXP (operands[1], 1));
>> + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
>> + }
>> +)
>> +
>> (define_insn "*csinc2<mode>_insn"
>> [(set (match_operand:GPI 0 "register_operand" "=r")
>> (plus:GPI (match_operator:GPI 2 "aarch64_comparison_operator"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/fcsel.c
>> b/gcc/testsuite/gcc.target/aarch64/fcsel.c
>> new file mode 100644
>> index 0000000..9c5431a
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/fcsel.c
>> @@ -0,0 +1,20 @@
>> +/* { dg-do compile } */
>> +/* { dg-options " -O2 " } */
>> +
>> +float f1 (float a, float b, float c, float d)
>> +{
>> + if (a > 0.0)
>> + return c;
>> + else
>> + return 2.0;
>> +}
>> +
>> +double f2 (double a, double b, double c, double d)
>> +{
>> + if (a > b)
>> + return c;
>> + else
>> + return d;
>> +}
>> +
>> +/* { dg-final { scan-assembler-times "\tfcsel" 2 } } */
