Index: libgcc/config/rs6000/linux-unwind.h =================================================================== --- libgcc/config/rs6000/linux-unwind.h (revision 212339) +++ libgcc/config/rs6000/linux-unwind.h (working copy) @@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind #ifdef __SPE__ for (i = 14; i < 32; i++) { - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET; - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET; + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset = (long) ®s->vregs - new_cfa + 4 * i; } #endif Index: gcc/testsuite/gcc.target/powerpc/pr60102.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr60102.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr60102.c (revision 0) @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-options "-mcpu=8548 -mspe -mabi=spe -g -mfloat-gprs=double" } */ + +double +pr60102 (double x, int m) +{ + double y; + y = m % 2 ? x : 1; + return y; +} Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 212339) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -30930,13 +30930,13 @@ rs6000_dwarf_register_span (rtx reg) { if (BYTES_BIG_ENDIAN) { - parts[2 * i] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); parts[2 * i + 1] = gen_rtx_REG (SImode, regno); } else { parts[2 * i] = gen_rtx_REG (SImode, regno); - parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); } } @@ -30956,7 +30956,7 @@ rs6000_init_dwarf_reg_sizes_extra (tree rtx mem = gen_rtx_MEM (BLKmode, addr); rtx value = gen_int_mode (4, mode); - for (i = 1201; i < 1232; i++) + for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++) { int column = DWARF_REG_TO_UNWIND_COLUMN (i); HOST_WIDE_INT offset @@ -31013,9 +31013,8 @@ rs6000_dbx_register_number (unsigned int return 99; if (regno == SPEFSCR_REGNO) return 612; - /* SPE high reg number. We get these values of regno from - rs6000_dwarf_register_span. */ - gcc_assert (regno >= 1200 && regno < 1232); + if (SPE_HIGH_REGNO_P (regno)) + return regno - FIRST_SPE_HIGH_REGNO + 1200; return regno; } Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 212339) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -929,13 +929,14 @@ enum data_align { align_abi, align_opt, The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ -#define FIRST_PSEUDO_REGISTER 117 +#define FIRST_PSEUDO_REGISTER 149 /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 -/* Add 32 dwarf columns for synthetic SPE registers. */ -#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32) +/* SPE high registers added as hard regs. + The 3 HTM registers aren't included in DWARF_FRAME_REGISTERS */ +#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) /* The SPE has an additional 32 synthetic registers, with DWARF debug info numbering for these registers starting at 1200. While eh_frame @@ -951,13 +952,14 @@ enum data_align { align_abi, align_opt, We must map them here to avoid huge unwinder tables mostly consisting of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) + ((r) >= FIRST_SPE_HIGH_REGNO ? ((r) - FIRST_SPE_HIGH_REGNO + (DWARF_FRAME_REGISTERS - 32)) : (r)) /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) /* Use gcc hard register numbering for eh_frame. */ -#define DWARF_FRAME_REGNUM(REGNO) (REGNO) +#define DWARF_FRAME_REGNUM(REGNO) \ + ((REGNO) >= 1200 ? ((REGNO) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (REGNO)) /* Map register numbers held in the call frame info that gcc has collected using DWARF_FRAME_REGNUM to those that should be output in @@ -991,7 +993,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1, 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1, \ + /* SPE High registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* 1 for registers not available across function calls. @@ -1011,7 +1016,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1, 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1, \ + /* SPE High registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that @@ -1030,7 +1038,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 \ - , 0, 0, 0, 0, 0, 0 \ + , 0, 0, 0, 0, 0, 0, \ + /* SPE High registers. */ \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) @@ -1113,7 +1124,10 @@ enum data_align { align_abi, align_opt, 96, 95, 94, 93, 92, 91, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 109, 110, \ - 111, 112, 113, 114, 115, 116 \ + 111, 112, 113, 114, 115, 116, \ + 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \ + 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ + 141, 142, 143, 144, 145, 146, 147, 148 \ } /* True if register is floating-point. */ @@ -1135,6 +1149,9 @@ enum data_align { align_abi, align_opt, /* PAIRED SIMD registers are just the FPRs. */ #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) +/* True if register is an SPE High register. */ +#define SPE_HIGH_REGNO_P(N) ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO) + /* True if register is the CA register. */ #define CA_REGNO_P(N) ((N) == CA_REGNO) @@ -1348,6 +1365,7 @@ enum reg_class CR_REGS, NON_FLOAT_REGS, CA_REGS, + SPE_HIGH_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -1379,6 +1397,7 @@ enum reg_class "CR_REGS", \ "NON_FLOAT_REGS", \ "CA_REGS", \ + "SPE_HIGH_REGS", \ "ALL_REGS" \ } @@ -1386,30 +1405,31 @@ enum reg_class This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ -#define REG_CLASS_CONTENTS \ -{ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ - { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ - { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ - { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \ - { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ - { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \ - { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ - { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ - { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ - { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ - { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \ +#define REG_CLASS_CONTENTS \ +{ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ + { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, /* BASE_REGS */ \ + { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, /* GENERAL_REGS */ \ + { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ + { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, /* ALTIVEC_REGS */ \ + { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, /* VSX_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, /* VRSAVE_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, /* VSCR_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, /* SPE_ACC_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, /* SPEFSCR_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, /* SPR_REGS */ \ + { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, /* NON_SPECIAL_REGS */ \ + { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* LINK_REGS */ \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* CTR_REGS */ \ + { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ + { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, /* SPECIAL_REGS */ \ + { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \ + { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* CR0_REGS */ \ + { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, /* CR_REGS */ \ + { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, /* NON_FLOAT_REGS */ \ + { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* CA_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0xfff00000, 0x000fffff }, /* SPE_HIGH_REGS */ \ + { 0xffffffff, 0xffffffff, 0xfffffffe, 0xfff7ffff, 0x000fffff } /* ALL_REGS */ \ } /* The same information, inverted: @@ -2341,6 +2361,39 @@ extern char rs6000_reg_names[][8]; /* re &rs6000_reg_names[114][0], /* tfhar */ \ &rs6000_reg_names[115][0], /* tfiar */ \ &rs6000_reg_names[116][0], /* texasr */ \ + \ + &rs6000_reg_names[117][0], /* SPE rh0 */ \ + &rs6000_reg_names[118][0], /* SPE rh1 */ \ + &rs6000_reg_names[119][0], /* SPE rh2 */ \ + &rs6000_reg_names[120][0], /* SPE rh3 */ \ + &rs6000_reg_names[121][0], /* SPE rh4 */ \ + &rs6000_reg_names[122][0], /* SPE rh5 */ \ + &rs6000_reg_names[123][0], /* SPE rh6 */ \ + &rs6000_reg_names[124][0], /* SPE rh7 */ \ + &rs6000_reg_names[125][0], /* SPE rh8 */ \ + &rs6000_reg_names[126][0], /* SPE rh9 */ \ + &rs6000_reg_names[127][0], /* SPE rh10 */ \ + &rs6000_reg_names[128][0], /* SPE rh11 */ \ + &rs6000_reg_names[129][0], /* SPE rh12 */ \ + &rs6000_reg_names[130][0], /* SPE rh13 */ \ + &rs6000_reg_names[131][0], /* SPE rh14 */ \ + &rs6000_reg_names[132][0], /* SPE rh15 */ \ + &rs6000_reg_names[133][0], /* SPE rh16 */ \ + &rs6000_reg_names[134][0], /* SPE rh17 */ \ + &rs6000_reg_names[135][0], /* SPE rh18 */ \ + &rs6000_reg_names[136][0], /* SPE rh19 */ \ + &rs6000_reg_names[137][0], /* SPE rh20 */ \ + &rs6000_reg_names[138][0], /* SPE rh21 */ \ + &rs6000_reg_names[139][0], /* SPE rh22 */ \ + &rs6000_reg_names[140][0], /* SPE rh22 */ \ + &rs6000_reg_names[141][0], /* SPE rh24 */ \ + &rs6000_reg_names[142][0], /* SPE rh25 */ \ + &rs6000_reg_names[143][0], /* SPE rh26 */ \ + &rs6000_reg_names[144][0], /* SPE rh27 */ \ + &rs6000_reg_names[145][0], /* SPE rh28 */ \ + &rs6000_reg_names[146][0], /* SPE rh29 */ \ + &rs6000_reg_names[147][0], /* SPE rh30 */ \ + &rs6000_reg_names[148][0], /* SPE rh31 */ \ } /* Table of additional register names to use in user input. */ @@ -2396,7 +2449,17 @@ extern char rs6000_reg_names[][8]; /* re {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ /* Transactional Memory Facility (HTM) Registers. */ \ - {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} } + {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \ + /* SPE high registers */ \ + {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \ + {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \ + {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \ + {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \ + {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \ + {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \ + {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \ + {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \ +} /* This is how to output an element of a case-vector that is relative. */ Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 212339) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -56,6 +56,8 @@ (TFHAR_REGNO 114) (TFIAR_REGNO 115) (TEXASR_REGNO 116) + (FIRST_SPE_HIGH_REGNO 117) + (LAST_SPE_HIGH_REGNO 148) ]) ;;