Hello, With this patch we'd like to start merge process of avx-512vlbwdq branch into main trunk.
This patch introduces new switch `-mavx512dq' Bootstrapped. Is it ok for trunk? * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512DQ_SET): Define. (OPTION_MASK_ISA_AVX512DQ_UNSET): Ditto. (ix86_handle_option): Handle OPT_mavx512dq. * config/i386/cpuid.h (bit_AVX512DQ): Define. * config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512dq, set -mavx512dq accordingly. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_AVX512DQ. * config/i386/i386.c (ix86_target_string): Handle -mavx512dq. (ix86_option_override_internal): Define PTA_AVX512DQ, handle PTA_AVX512DQ and OPTION_MASK_ISA_AVX512DQ. (ix86_valid_target_attribute_inner_p): Handle OPT_mavx512dq. * config/i386/i386.h (TARGET_AVX512DQ): Define. (TARGET_AVX512DQ_P(x)): Ditto. * config/i386/i386.opt: Add mavx512dq. -- Thanks, K diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 3012783..3db1535 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -65,6 +65,8 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512ER_SET \ (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512DQ_SET \ + (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED @@ -156,6 +158,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER +#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED @@ -393,6 +396,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mavx512dq: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 7ac22a1..dc65053 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -73,6 +73,7 @@ #define bit_BMI2 (1 << 8) #define bit_RTM (1 << 11) #define bit_AVX512F (1 << 16) +#define bit_AVX512DQ (1 << 17) #define bit_RDSEED (1 << 18) #define bit_ADX (1 << 19) #define bit_CLFLUSHOPT (1 << 23) diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 4cd0b3d..8ff49ac 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -411,6 +411,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0; unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0; unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0; + unsigned int has_avx512dq = 0; bool arch; @@ -488,6 +489,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_avx512cd = ebx & bit_AVX512CD; has_sha = ebx & bit_SHA; has_clflushopt = ebx & bit_CLFLUSHOPT; + has_avx512dq = ebx & bit_AVX512DQ; has_prefetchwt1 = ecx & bit_PREFETCHWT1; } @@ -900,6 +902,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt"; const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec"; const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves"; + const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq"; options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, sse4a, cx16, sahf, movbe, aes, sha, pclmul, @@ -908,7 +911,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx, fxsr, xsave, xsaveopt, avx512f, avx512er, avx512cd, avx512pf, prefetchwt1, clflushopt, - xsavec, xsaves, NULL); + xsavec, xsaves, avx512dq, NULL); } done: diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 2c05cec..c0c0f3d 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -345,6 +345,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__AVX512CD__"); if (isa_flag & OPTION_MASK_ISA_AVX512PF) def_or_undef (parse_in, "__AVX512PF__"); + if (isa_flag & OPTION_MASK_ISA_AVX512DQ) + def_or_undef (parse_in, "__AVX512DQ__"); if (isa_flag & OPTION_MASK_ISA_FMA) def_or_undef (parse_in, "__FMA__"); if (isa_flag & OPTION_MASK_ISA_RTM) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 542945f..d5f44ec 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2593,6 +2593,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, { "-mavx512er", OPTION_MASK_ISA_AVX512ER }, { "-mavx512cd", OPTION_MASK_ISA_AVX512CD }, { "-mavx512pf", OPTION_MASK_ISA_AVX512PF }, + { "-mavx512dq", OPTION_MASK_ISA_AVX512DQ }, { "-msse4a", OPTION_MASK_ISA_SSE4A }, { "-msse4.2", OPTION_MASK_ISA_SSE4_2 }, { "-msse4.1", OPTION_MASK_ISA_SSE4_1 }, @@ -3123,6 +3124,7 @@ ix86_option_override_internal (bool main_args_p, #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47) #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48) #define PTA_XSAVES (HOST_WIDE_INT_1 << 49) +#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50) #define PTA_CORE2 \ (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \ @@ -3689,6 +3691,9 @@ ix86_option_override_internal (bool main_args_p, if (processor_alias_table[i].flags & PTA_XSAVES && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVES)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES; + if (processor_alias_table[i].flags & PTA_AVX512DQ + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ; if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) x86_prefetch_sse = true; @@ -4545,6 +4550,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], IX86_ATTR_ISA ("avx512pf", OPT_mavx512pf), IX86_ATTR_ISA ("avx512er", OPT_mavx512er), IX86_ATTR_ISA ("avx512cd", OPT_mavx512cd), + IX86_ATTR_ISA ("avx512dq", OPT_mavx512dq), IX86_ATTR_ISA ("mmx", OPT_mmmx), IX86_ATTR_ISA ("pclmul", OPT_mpclmul), IX86_ATTR_ISA ("popcnt", OPT_mpopcnt), diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 9e3ef94..d249879 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -71,6 +71,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) #define TARGET_AVX512CD TARGET_ISA_AVX512CD #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) +#define TARGET_AVX512DQ TARGET_ISA_AVX512DQ +#define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) #define TARGET_FMA TARGET_ISA_FMA #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) #define TARGET_SSE4A TARGET_ISA_SSE4A diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index dc1302c..daeb150 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -641,6 +641,10 @@ mavx512cd Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation +mavx512dq +Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation + mfma Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation