On Mon, Sep 01, 2014 at 10:41:43AM -0600, Jeff Law wrote: > On 08/31/14 06:18, Segher Boessenkool wrote: > >On Fri, Aug 29, 2014 at 11:58:37PM -0600, Jeff Law wrote: > >>One could argue that this mess is a result of trying to optimize a reg > >>that is set more than once. Though I guess that might be a bit of a > >>big hammer. > > > >It works fine in other cases, and is quite beneficial for e.g. optimising > >instruction sequences that set a fixed carry register twice. > How common is that?
I meant once setting the reg, and then using and clobbering it in another insn. This is quite common -- on some targets the add-with-carry insns are used for scc things too. You could say all cases where combine can do something with this should have been optimised earlier, but that is not the case today. > While we don't have any formal SSA-like properties in RTL, we're > certainly better off if we can avoid unnecessary cases where a single > pseudo is set more than once Note that in this case we're talking about a hard register, not a pseudo. > and these days I wouldn't expect too many > cases where have multiple sets appearing in a dep chain that can be > processed by combine (and if we do one could easily argue those dep > chains should be simplified). For pseudos I of course agree with that :-) Segher
