On 12 August 2014 15:43, Alan Lawrence <alan.lawre...@arm.com> wrote: > This patch adds SIMD register variants for and, ior, xor and not - similarly > to add/sub, the H/W supports it, and it'll be more efficient if the values > are there already, e.g. if passed as [u]int64x1_t parameters. > > gcc/ChangeLog: > > * config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2): > Add SIMD-register variant. > * config/aarch64/iterators.md (Vbtype): Add value for SI.
OK /Marcus
