On 10/06/14 19:31, Bin.Cheng wrote:
On Tue, Oct 7, 2014 at 1:20 AM, Mike Stump <mikest...@comcast.net> wrote:
On Oct 6, 2014, at 4:32 AM, Richard Biener <richard.guent...@gmail.com> wrote:
On Mon, Oct 6, 2014 at 11:57 AM, Bin.Cheng <amker.ch...@gmail.com> wrote:
How many merging opportunities does sched2 undo again? ISTR it
has the tendency of pushing stores down and loads up.
So, the pass works by merging 2 or more loads into 1 load (at least on my
port). sched2 would need to rip apart 1 load into 2 loads to be able to undo
the real work. The non-real work, doesn't matter any. Can sched2 rip apart a
single load?
On ARM and AARCH64, the two merged load/store are transformed into
single parallel insn by the following peephole2 pass, so that sched2
would not undo the fusion work. I though sched2 works on the basis of
instructions, and it isn't good practice to have sched2 do split work.
It's certainly advantageous for sched2 to split insns that generate
multiple instructions. Running after register allocation, sched2 is
ideal for splitting because the we know the alternative for each insn
and thus we can (possibly for the first time) accurately know if a
particular insn will generate multiple assembly instructions.
If the port has a splitter to rip apart a douple-word load into
single-word loads, then we'd obviously only want to do that in cases
where the double-word load actually generates > 1 assembly instruction.
Addressing issues in that space seems out of scope for Bin's work to me,
except perhaps for such issues on aarch64/arm which are Bin's primary
concerns.
jeff
