When I did the original power7 work, I put the reload handlers into vector.md,
since they were only used for vector types. Since they are now more general, I
am moving these insns from vector.md to rs6000.md. Is this patch acceptable to
be checked in once the PowerPC boostraps again.
2014-11-11 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_R): Move secondary reload support
insns to rs6000.md from vector.md.
(reload_<VEC_R:mode>_<P:mptrsize>_store): Likewise.
(reload_<VEC_R:mode>_<P:mptrsize>_load): Likewise.
(vec_reload_and_plus_<mptrsize>): Likewise.
* config/rs6000/rs6000.md (RELOAD): New mode iterator for all of
the types that have secondary reload address support to load up a
base register.
(reload_<RELOAD:mode>_<P:mptrsize>_store): Move the reload
handlers here from vector.md, and expand the types we generate
reload handlers for.
(reload_<RELOAD:mode>_<P:mptrsize>_load): Likewise.
(vec_reload_and_plus_<mptrsize>): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/vector.md
===================================================================
--- gcc/config/rs6000/vector.md (revision 217384)
+++ gcc/config/rs6000/vector.md (revision 217385)
@@ -53,10 +53,6 @@ (define_mode_iterator VEC_E [V16QI V8HI
;; Vector modes for 64-bit base types
(define_mode_iterator VEC_64 [V2DI V2DF])
-;; Vector reload iterator
-(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
- SF SD SI DF DD DI TI])
-
;; Base type from vector mode
(define_mode_attr VEC_base [(V16QI "QI")
(V8HI "HI")
@@ -185,49 +181,6 @@ (define_expand "vector_altivec_store_<mo
-;; Reload patterns for vector operations. We may need an additional base
-;; register to convert the reg+offset addressing to reg+reg for vector
-;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index
-;; register for gpr registers.
-(define_expand "reload_<VEC_R:mode>_<P:mptrsize>_store"
- [(parallel [(match_operand:VEC_R 0 "memory_operand" "m")
- (match_operand:VEC_R 1 "gpc_reg_operand" "r")
- (match_operand:P 2 "register_operand" "=&b")])]
- "<P:tptrsize>"
-{
- rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
- DONE;
-})
-
-(define_expand "reload_<VEC_R:mode>_<P:mptrsize>_load"
- [(parallel [(match_operand:VEC_R 0 "gpc_reg_operand" "=&r")
- (match_operand:VEC_R 1 "memory_operand" "m")
- (match_operand:P 2 "register_operand" "=&b")])]
- "<P:tptrsize>"
-{
- rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
- DONE;
-})
-
-;; Reload sometimes tries to move the address to a GPR, and can generate
-;; invalid RTL for addresses involving AND -16. Allow addresses involving
-;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
-
-(define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
- [(set (match_operand:P 0 "gpc_reg_operand" "=b")
- (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
- (match_operand:P 2 "reg_or_cint_operand" "rI"))
- (const_int -16)))]
- "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (plus:P (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (and:P (match_dup 0)
- (const_int -16)))])
-
;; Generic floating point vector arithmetic support
(define_expand "add<mode>3"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 217384)
+++ gcc/config/rs6000/rs6000.md (revision 217385)
@@ -589,6 +589,12 @@ (define_mode_attr BOOL_REGS_UNARY [(TI "
(V2DI "wa,v,r,0,0")
(V2DF "wa,v,r,0,0")
(V1TI "wa,v,r,0,0")])
+
+;; Reload iterator for creating the function to allocate a base register to
+;; supplement addressing modes.
+(define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
+ SF SD SI DF DD DI TI PTI])
+
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
@@ -8415,6 +8421,50 @@ (define_expand "reload_<mode>_load"
})
+;; Reload patterns for various types using the vector registers. We may need
+;; an additional base register to convert the reg+offset addressing to reg+reg
+;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
+;; index register for gpr registers.
+(define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
+ [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
+ (match_operand:RELOAD 1 "gpc_reg_operand" "wa")
+ (match_operand:P 2 "register_operand" "=b")])]
+ "<P:tptrsize>"
+{
+ rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
+ DONE;
+})
+
+(define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
+ [(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
+ (match_operand:RELOAD 1 "memory_operand" "m")
+ (match_operand:P 2 "register_operand" "=b")])]
+ "<P:tptrsize>"
+{
+ rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
+ DONE;
+})
+
+
+;; Reload sometimes tries to move the address to a GPR, and can generate
+;; invalid RTL for addresses involving AND -16. Allow addresses involving
+;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
+
+(define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=b")
+ (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
+ (match_operand:P 2 "reg_or_cint_operand" "rI"))
+ (const_int -16)))]
+ "TARGET_ALTIVEC && (reload_in_progress || reload_completed)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (plus:P (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (and:P (match_dup 0)
+ (const_int -16)))])
+
;; Power8 merge instructions to allow direct move to/from floating point
;; registers in 32-bit mode. We use TF mode to get two registers to move the
;; individual 32-bit parts across. Subreg doesn't work too well on the TF
