This means we can no longer add GPR0+imm. Register allocation will have
to use a different register.
2014-12-08 Segher Boessenkool <seg...@kernel.crashing.org>
gcc/
PR target/64180
* config/rs6000/rs6000.md (*add<mode>3_internal1): Remove addic
alternative.
---
gcc/config/rs6000/rs6000.md | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6f4bafb..1647f8b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1491,17 +1491,14 @@ (define_expand "add<mode>3"
}
})
-;; Discourage ai/addic because of carry but provide it in an alternative
-;; allowing register zero as source.
(define_insn "*add<mode>3_internal1"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
- (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
- (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r")
+ (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b")
+ (match_operand:GPR 2 "add_operand" "r,I,L")))]
"!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P
(GET_MODE (operands[1]))"
"@
add %0,%1,%2
addi %0,%1,%2
- addic %0,%1,%2
addis %0,%1,%v2"
[(set_attr "type" "add")])
--
1.8.1.4
