On 5/21/2026 9:40 PM, Andrew Pinski wrote:
On Thu, May 21, 2026 at 8:31 PM Jeffrey Law
<[email protected]> wrote:
On 5/18/2026 9:39 PM, [email protected] wrote:
Dear contributor,
Our automatic CI has detected problems related to your patch(es). Please find
some details below.
In aarch64 native, after:
| commit gcc-17-577-gbc19036af435
| Author: Jeff Law <[email protected]>
| Date: Mon May 18 15:17:27 2026 -0600
|
| [RISC-V] Improve ext-dce's live bit tracking for IOR/AND with a
constant argument
|
| Investigation of a regression with some RISC-V target changes exposed
a clear
| missed optimization in ext-dce.c
|
| ... 67 lines of the commit log omitted.
Produces 2 regressions:
|
| regressions.sum:
| Running gcc:gcc.target/aarch64/aarch64.exp ...
| FAIL: gcc.target/aarch64/tbz_1.c check-function-bodies g1
| FAIL: gcc.target/aarch64/tbz_1.c check-function-bodies g2
I've reproduced this locally. I haven't gotten into the debug cycle
yet, but wanted folks to know it's mine AFAICT to avoid duplicating
debugging efforts.
I think the fix is just a testcase fix.
Currently the testcase has:
** tbnz w[0-9]+, #?0, .L([0-9]+)
But that should just can be:
** tbnz [wx][0-9]+, #?0, .L([0-9]+)
to match both x0 and w0 there. But are valid in this case with bit 0.
For both g1 and g2.
Yea, highly likely, but I wanted to look closely at it to make sure I
hadn't missed anything. Time is just very limited right now due to a
personal issue.
