Hi,
I have a question about the scheduler. Forgive me if I'm totally
missing the point here, this scheduling business is not my thing ;-)
Consider the following snippet that I've derived from PR17808 with a
few hacks in the compiler to renumber insns and dump RTL with all the
dependencies before scheduling. There is a predicate register that
gets set, then a few cond_exec insns, then a jump, and finally a set
using some of the registers that may be set by the cond_exec insns.
This is the RTL before scheduling:
(insn 8 7 9 0 (set (reg:BI 262 p6 [353])
(ne:BI (reg/v:SI 15 r15 [orig:348 b1 ] [348])
(const_int 0 [0x0]))) 226 {*cmpsi_normal} (insn_list:REG_DEP_TRUE 7
(nil))
(nil))
(insn 9 8 10 0 (cond_exec (ne (reg:BI 262 p6 [353])
(const_int 0 [0x0]))
(set (reg/v/f:DI 14 r14 [orig:347 t16 ] [347])
(reg/v/f:DI 112 r32 [orig:351 t ] [351]))) 680
{sync_lock_releasedi+5} (insn_list:REG_DEP_TRUE 8 (nil))
(nil))
(insn 10 9 11 0 (cond_exec (ne (reg:BI 262 p6 [353])
(const_int 0 [0x0]))
(set (reg/v:SI 17 r17 [orig:346 iftmp ] [346])
(const_int 0 [0x0]))) 679 {sync_lock_releasedi+4}
(insn_list:REG_DEP_TRUE 8 (nil))
(nil))
(insn 11 10 12 0 (cond_exec (ne (reg:BI 262 p6 [353])
(const_int 0 [0x0]))
(set (reg/v:SI 16 r16 [orig:349 i ] [349])
(const_int 0 [0x0]))) 679 {sync_lock_releasedi+4}
(insn_list:REG_DEP_TRUE 8 (nil))
(nil))
(jump_insn 12 11 13 0 (set (pc)
(if_then_else (eq (reg:BI 262 p6 [353])
(const_int 0 [0x0]))
(label_ref:DI 39)
(pc))) 235 {*br_true} (insn_list:REG_DEP_TRUE 8
(insn_list:REG_DEP_ANTI 7 (nil)))
(expr_list:REG_DEAD (reg:BI 262 p6 [353])
(expr_list:REG_BR_PROB (const_int 3300 [0xce4])
(nil))))
;; End of basic block 0, registers live:
1 [r1] 12 [r12] 14 [r14] 15 [r15] 16 [r16] 17 [r17] 18 [r18] 112 [r32] 320
[b0] 331 [ar.pfs]
;; Start of basic block 1, registers live: 1 [r1] 12 [r12] 14 [r14] 16 [r16] 17
[r17] 18 [r18] 112 [r32] 320 [b0] 331 [ar.pfs]
(note 13 12 14 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(insn 14 13 15 1 (set (mem:SI (reg/v/f:DI 14 r14 [orig:347 t16 ] [347]) [2 S4
A32])
(reg/v:SI 17 r17 [orig:346 iftmp ] [346])) 4 {*movsi_internal}
(insn_list:REG_DEP_TRUE 12 (insn_list:REG_DEP_ANTI 7 (nil)))
(expr_list:REG_DEAD (reg/v:SI 17 r17 [orig:346 iftmp ] [346])
(expr_list:REG_DEAD (reg/v/f:DI 14 r14 [orig:347 t16 ] [347])
(nil))))
Then the ia64 machine-reorg scheduler gets to work, and it produces:
(insn:TI 8 70 12 0 (set (reg:BI 262 p6 [353])
(ne:BI (reg/v:SI 15 r15 [orig:348 b1 ] [348])
(const_int 0 [0x0]))) 226 {*cmpsi_normal} (insn_list:REG_DEP_TRUE 7
(nil))
(nil))
(jump_insn 12 8 77 0 (set (pc)
(if_then_else (eq (reg:BI 262 p6 [353])
(const_int 0 [0x0]))
(label_ref:DI 39)
(pc))) 235 {*br_true} (insn_list:REG_DEP_TRUE 8
(insn_list:REG_DEP_ANTI 7 (nil)))
(expr_list:REG_DEAD (reg:BI 262 p6 [353])
(expr_list:REG_BR_PROB (const_int 3300 [0xce4])
(nil))))
(note 77 12 69 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(... other non-jump, non-cond_exec insns ...)
(insn 14 15 16 1 (set (mem:SI (reg/v/f:DI 14 r14 [orig:347 t16 ] [347]) [2 S4
A32])
(reg/v:SI 17 r17 [orig:346 iftmp ] [346])) 4 {*movsi_internal}
(insn_list:REG_DEP_TRUE 12 (insn_list:REG_DEP_ANTI 7 (nil)))
(expr_list:REG_DEAD (reg/v:SI 17 r17 [orig:346 iftmp ] [346])
(expr_list:REG_DEAD (reg/v/f:DI 14 r14 [orig:347 t16 ] [347])
(nil))))
(... other non-jump, non-cond_exec insns ...)
(insn 10 18 11 1 (cond_exec (ne (reg:BI 262 p6 [353])
(const_int 0 [0x0]))
(set (reg/v:SI 17 r17 [orig:346 iftmp ] [346])
(const_int 0 [0x0]))) 679 {sync_lock_releasedi+4}
(insn_list:REG_DEP_TRUE 8 (nil))
(nil))
(insn 11 10 67 1 (cond_exec (ne (reg:BI 262 p6 [353])
(const_int 0 [0x0]))
(set (reg/v:SI 16 r16 [orig:349 i ] [349])
(const_int 0 [0x0]))) 679 {sync_lock_releasedi+4}
(insn_list:REG_DEP_TRUE 8 (nil))
(nil))
(... other non-jump, non-cond_exec insns ...)
(insn:TI 9 60 65 1 (cond_exec (ne (reg:BI 262 p6 [353])
(const_int 0 [0x0]))
(set (reg/v/f:DI 14 r14 [orig:347 t16 ] [347])
(reg/v/f:DI 112 r32 [orig:351 t ] [351]))) 680
{sync_lock_releasedi+5} (insn_list:REG_DEP_TRUE 8 (nil))
(nil))
Notice how the conditional sets of r14 and r17 in insns 9 and 10 have
been moved past insn 14, which uses these registers. Shouldn't there
be true dependencies on insns 9 and 10 for insn 14?
Gr.
Steven
