Hi,
I'm trying to figure out how much effort it would take to make
dbr_schedule CFG aware. One of the issues I'm running into is
that the RTL CFG stuff doesn't support SEQUENCEs at all. So if
I have a delay slot filled, e.g.,
(sequence [
(jump_insn (...)) ;; The branch with delay slots
(insn (...)) ;; An insn in a delay slot
])
verify_flow_info immediately dies on this because the last insn
in a basic block is not a branch instruction. It sees just the
sequence and not the instructions in it.
Now I could add some kind of flag "reorg_completed" and go hack
all the RTL cfg routines to support SEQUENCEs. But I'd rather
not do that unless I'm really sure nobody thinks that is a Very
Bad Idea. ;-)
Thoughts?
Gr.
Steven
