On Fri, Apr 24, 2015 at 11:45 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich <enkovich....@gmail.com> 
> wrote:
>
>> I was looking into PR65105 and tried to generate SSE computation for a
>> simple 64bit  a + b + c sequence. Having no scalar integer instructions in
>> SSE I have to use vector variants.
>
> Is this approach really better that having two add/addc instructions?

FYI, V1DI mode was introduced because XMM shift insn were used to
shift DImode values. The cost of moves from/to integer DImode reg pair
was disastrous.

Uros.

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