https://gcc.gnu.org/g:0f9ce736b8de5ff184a17555a9b89603b24e0ac8

commit r16-3247-g0f9ce736b8de5ff184a17555a9b89603b24e0ac8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Aug 18 00:18:52 2025 +0000

    Daily bump.

Diff:
---
 ChangeLog               |  5 +++++
 contrib/ChangeLog       |  5 +++++
 gcc/ChangeLog           | 42 +++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |  2 +-
 gcc/testsuite/ChangeLog | 56 +++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 109 insertions(+), 1 deletion(-)

diff --git a/ChangeLog b/ChangeLog
index fe25fde94896..0cbf930f08f7 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2025-08-17  Filip Kastl  <fka...@suse.cz>
+
+       * MAINTAINERS: Switch around Andrew Pinski's entries in
+       Contributing under DCO.
+
 2025-08-16  Mikael Pettersson  <mikpeli...@gmail.com>
 
        * MAINTAINERS: Add myself to write after approval.
diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 5370de647432..691203f9036b 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,8 @@
+2025-08-17  Filip Kastl  <fka...@suse.cz>
+
+       * check-MAINTAINERS.py: Document the way the script sorts
+       entries.
+
 2025-08-07  Tobias Burnus  <tbur...@baylibre.com>
 
        PR other/120237
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8843cda665f8..7245e5a386ef 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,45 @@
+2025-08-17  Austin Law  <austink...@gmail.com>
+
+       PR target/121213
+       * config/riscv/sync.md (amo_atomic_exchange<mode>): Allow
+       (const_int 0) as input operand. Do not tie input to output.
+       No longer earlyclobber the output.
+
+2025-08-17  Artemiy Volkov  <artem...@acm.org>
+
+       * regrename.cc (scan_rtx_reg): Handle fused insn pairs.
+
+2025-08-17  Jan Dubiec  <j...@o2.pl>
+
+       PR target/109324
+       * config/h8300/addsub.md: Explicitly specify mode for plus operation.
+       * config/h8300/jumpcall.md: Explicitly specify modes for eq and
+       match_operand operations.
+       * config/h8300/testcompare.md: Explicitly specify modes for eq, ltu
+       and compare operations.
+
+2025-08-17  Artemiy Volkov  <artem...@acm.org>
+
+       * ira-conflicts.cc (add_insn_allocno_copies): Handle fused insn pairs.
+       * rtl.h (single_output_fused_pair_p): Declare new function.
+       * rtlanal.cc (single_output_fused_pair_p): Define it.
+
+2025-08-17  Dimitar Dimitrov  <dimi...@dinux.eu>
+
+       PR target/121538
+       * config/riscv/arch-canonicalize (parse_dep_exts):
+       Match condition block up to closing brace.
+       (test_parse_long_condition_block): New test.
+
+2025-08-17  H.J. Lu  <hjl.to...@gmail.com>
+
+       PR target/121541
+       * config/i386/i386-options.cc
+       (ix86_valid_target_attribute_inner_p): Add target("80387")
+       attribute.  Set the mask bit in opts_set->x_target_flags if the
+       mask bit in opts->x_target_flags is updated.
+       * doc/extend.texi: Document target("80387") function attribute.
+
 2025-08-17  Pan Li  <pan2...@intel.com>
 
        * config/riscv/autovec-opt.md: Add supported insn
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 183ec5b707a3..31dab4332477 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250817
+20250818
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d15b154d6043..d35caa7cb38b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,59 @@
+2025-08-17  Austin Law  <austink...@gmail.com>
+
+       PR target/121213
+       * gcc.target/riscv/amo/pr121213.c: New test.
+
+2025-08-17  dragan.mladjenovic  <dragan.mladjeno...@rt-rk.com>
+
+       * gcc.target/mips/tls-1.c: New file.
+
+2025-08-17  Matthew Fortune  <matthew.fort...@imgtec.com>
+
+       * gcc.target/mips/call-clobbered-1.c: Use HAS_LDC ghost
+       option instead of isa>=2.
+
+2025-08-17  Andrew Bennett  <andrew.benn...@imgtec.com>
+
+       * gcc.target/mips/near-far-1.c: Fix tests properly for
+       compact-branches (jals and balc).
+       * gcc.target/mips/near-far-2.c: Likewise.
+       * gcc.target/mips/near-far-3.c: Likewise.
+       * gcc.target/mips/near-far-4.c: Likewise.
+
+2025-08-17  Jeff Law  <j...@ventanamicro.com>
+
+       * gcc.target/mips/call-clobbered-2.c: Add a NOMIPS16 attribute.
+       * gcc.target/mips/call-clobbered-3.c: Likewise.
+       * gcc.target/mips/call-clobbered-5.c: Likewise.
+       * gcc.target/mips/ds-schedule-2.c: Add an -mno-mips16 option.
+       * gcc.target/mips/interrupt_handler-bug-1.c: Same as
+       call-clobbered-*.c tests.
+       * gcc.target/mips/movdf-1.c: Likewise.
+       * gcc.target/mips/movdf-2.c: Likewise.
+       * gcc.target/mips/movdf-3.c: Likewise.
+       * gcc.target/mips/msa-builtins.c: Same as ds-schedule-2.c.
+       Remove a NOMIPS16 attribute from builtins.
+       * gcc.target/mips/msa.c: Likewise.
+
+2025-08-17  Matthew Fortune  <matthew.fort...@imgtec.com>
+
+       * gcc.target/mips/insn-casesi.c: Require mips16 support but
+       not the command line option.
+       * gcc.target/mips/insn-tablejump.c: Force o32 ABI as
+       we do not really support n32/n64 microMIPS.  Require micromips
+       support but not the command line option.
+
+2025-08-17  H.J. Lu  <hjl.to...@gmail.com>
+
+       PR target/121541
+       * gcc.target/i386/pr121541-1a.c: New test.
+       * gcc.target/i386/pr121541-1b.c: Likewise.
+       * gcc.target/i386/pr121541-2.c: Likewise.
+       * gcc.target/i386/pr121541-3.c: Likewise.
+       * gcc.target/i386/pr121541-4.c: Likewise.
+       * gcc.target/i386/pr121541-5a.c: Likewise.
+       * gcc.target/i386/pr121541-5b.c: Likewise.
+
 2025-08-17  Nathaniel Shead  <nathanielosh...@gmail.com>
 
        PR c++/120503

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