https://gcc.gnu.org/g:2dfd2779e373dffaae9532d45267497a6246f661
commit r16-3385-g2dfd2779e373dffaae9532d45267497a6246f661
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Tue Aug 26 00:21:05 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 145 ++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/cp/ChangeLog | 14 +++++
gcc/testsuite/ChangeLog | 99 +++++++++++++++++++++++++++++++++
4 files changed, 259 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3c42fa209f54..dde7709d5a79 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,148 @@
+2025-08-26 Pan Li <pan2...@intel.com>
+
+ * config/riscv/vector.md (@pred_mul_plus_vx_<mode>): Add new pattern to
+ generate vmacc rtl.
+ (*pred_macc_<mode>_scalar_undef): Ditto.
+ * config/riscv/autovec-opt.md (*vmacc_vx_<mode>): Add new
+ pattern to match the vmacc vx combine.
+
+2025-08-25 Jakub Jelinek <ja...@redhat.com>
+
+ PR middle-end/121453
+ * omp-expand.cc (expand_omp_for_init_counts): Clear fd->loop.n2
+ before first zero count check if zero_iter1_bb is non-NULL upon
+ entry and fd->loop.n2 has not been written yet.
+
+2025-08-25 David Faust <david.fa...@oracle.com>
+
+ PR debug/121411
+ * dwarf2ctf.cc (gen_ctf_subrange_type): Use unsigned HWI for
+ array_num_elements. Fallback to CTF_K_UNKNOWN if the array
+ type has too many elements for CTF to represent.
+
+2025-08-25 Andrew Pinski <andrew.pin...@oss.qualcomm.com>
+
+ * tree-ssa-forwprop.cc (simplify_permutation): Boolify.
+ (pass_forwprop::execute): No longer handle 2 as the return
+ from simplify_permutation.
+
+2025-08-25 Andrew Pinski <andrew.pin...@oss.qualcomm.com>
+
+ * tree-ssa-forwprop.cc (forward_propagate_into_comparison): Boolify.
+ (pass_forwprop::execute): Don't handle return of 2 from
+ forward_propagate_into_comparison.
+
+2025-08-25 Andrew Pinski <andrew.pin...@oss.qualcomm.com>
+
+ * tree-ssa-forwprop.cc (remove_prop_source_from_use): Remove
+ return type.
+ (forward_propagate_into_comparison): Update dealing with
+ no return type of remove_prop_source_from_use.
+ (forward_propagate_into_gimple_cond): Likewise.
+ (simplify_permutation): Likewise.
+
+2025-08-25 Andrew Pinski <andrew.pin...@oss.qualcomm.com>
+
+ * tree-ssa-forwprop.cc (simplify_gimple_switch): Add simple_dce_worklist
+ argument. Mark the old index when doing the replacement.
+ (pass_forwprop::execute): Update call to simplify_gimple_switch.
+
+2025-08-25 Andrew Pinski <andrew.pin...@oss.qualcomm.com>
+
+ PR tree-optimization/121279
+ * gimple-fold.cc (gimple_needing_rewrite_undefined): Return
+ true for non mode precision boolean loads.
+ (rewrite_to_defined_unconditional): Handle non mode precision loads.
+
+2025-08-25 Andrew Pinski <andrew.pin...@oss.qualcomm.com>
+
+ * tree-ssa-loop-im.cc (execute_sm): Call
+ get_or_create_ssa_default_def for the new uninitialized
+ decl.
+
+2025-08-25 Takayuki 'January June' Suwa <jjsuwa_sys3...@yahoo.co.jp>
+
+ * config/xtensa/xtensa.md (addsi3, <u>mulhisi3, andsi3,
+ zero_extend<mode>si2, extendhisi2_internal, movsi_internal,
+ movhi_internal, movqi_internal, movsf_internal, ashlsi3_internal,
+ ashrsi3, lshrsi3, rotlsi3, rotrsi3):
+ Rewrite in compact syntax.
+
+2025-08-25 Takayuki 'January June' Suwa <jjsuwa_sys3...@yahoo.co.jp>
+
+ * config/xtensa/xtensa.md
+ (The auxiliary define_split for *masktrue_const_bitcmpl):
+ Use a more concise function call, i.e.,
+ (1 << GET_MODE_BITSIZE (mode)) - 1 is equivalent to
+ GET_MODE_MASK (mode).
+
+2025-08-25 Takayuki 'January June' Suwa <jjsuwa_sys3...@yahoo.co.jp>
+
+ * config/xtensa/xtensa.md (mode_bits):
+ New mode attribute.
+ (zero_extend<mode>si2): Use the appropriate mode iterator and
+ attribute to unify "zero_extend[hq]isi2" to this description.
+
+2025-08-25 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/121638
+ * tree-vect-stmts.cc (process_use): Do not make induction
+ PHI backedge values relevant.
+
+2025-08-25 Indu Bhagat <indu.bha...@oracle.com>
+ Claudiu Zissulescu <claudiu.zissulescu-iancule...@oracle.com>
+
+ * asan.h (HWASAN_TAG_SIZE): Use targetm.memtag.tag_bitsize.
+ * config/i386/i386.cc (ix86_memtag_tag_size): Rename to
+ ix86_memtag_tag_bitsize.
+ (TARGET_MEMTAG_TAG_SIZE): Renamed to TARGET_MEMTAG_TAG_BITSIZE.
+ * doc/tm.texi (TARGET_MEMTAG_TAG_SIZE): Likewise.
+ * doc/tm.texi.in (TARGET_MEMTAG_TAG_SIZE): Likewise.
+ * target.def (tag_size): Rename to tag_bitsize.
+ * targhooks.cc (default_memtag_tag_size): Rename to
+ default_memtag_tag_bitsize.
+ * targhooks.h (default_memtag_tag_size): Likewise.
+
+2025-08-25 Kito Cheng <kito.ch...@sifive.com>
+
+ * config/riscv/riscv-protos.h (riscv_init_cumulative_args): Change
+ fntype parameter from tree to const_tree.
+ * config/riscv/riscv.cc (riscv_init_cumulative_args): Likewise.
+ (riscv_function_value): Replace with new implementation that
+ conforms to TARGET_FUNCTION_VALUE hook signature.
+ (riscv_libcall_value): New function implementing TARGET_LIBCALL_VALUE.
+ (TARGET_FUNCTION_VALUE): Define.
+ (TARGET_LIBCALL_VALUE): Define.
+ * config/riscv/riscv.h (FUNCTION_VALUE): Remove.
+ (LIBCALL_VALUE): Remove.
+
+2025-08-25 Andi Kleen <a...@gcc.gnu.org>
+
+ * config/i386/i386-expand.cc (ix86_vgf2p8affine_shift_matrix):
+ New function to lookup shift/rotate matrixes for gf2p8affine.
+ * config/i386/i386-protos.h (ix86_vgf2p8affine_shift_matrix):
+ Declare new function.
+ * config/i386/i386.cc (ix86_shift_rotate_cost): Add cost model
+ for shift/rotate implemented using gf2p8affine.
+ * config/i386/sse.md (VI1_AVX512_3264): New mode iterator.
+ (<insn><mode>3): Add GFNI case for shift patterns.
+ (cond_<insn><mode>3): New pattern.
+ (<insn><mode>3<mask_name>): Dito.
+ (<insn>v16qi): New rotate pattern to handle XOP V16QI case
+ and GFNI.
+ (rotl<mode>3, rotr<mode>3): Exclude V16QI case.
+
+2025-08-25 Xi Ruoyao <xry...@xry111.site>
+
+ PR target/121634
+ * config/loongarch/simd.md (simd_maddw_evod_<mode>_<su>): Use
+ WVEC_HALF instead of WVEC for the mode of the sign_extend for
+ the rhs of multiplication.
+
+2025-08-25 Jeff Law <j...@ventanamicro.com>
+
+ * ifcvt.cc (noce_try_sign_bit_splat): Fix right shift computation.
+
2025-08-23 Sam James <s...@gentoo.org>
PR target/120933
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 33e9bdf83369..3d416de541bc 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250825
+20250826
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 7f5e82678fac..28c1447810a6 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,17 @@
+2025-08-25 Jakub Jelinek <ja...@redhat.com>
+
+ * pt.cc (finish_expansion_stmt): Implement C++ CWG3048
+ - Empty destructuring expansion statements. Don't error for
+ destructuring expansion stmts if sz is 0, don't call
+ fit_decomposition_lang_decl if n is 0 and pass NULL rather than
+ this_decomp to cp_finish_decl.
+
+2025-08-25 Jakub Jelinek <ja...@redhat.com>
+
+ PR c++/121601
+ * constexpr.cc (cxx_bind_parameters_in_call): Move break
+ if *jump_target before the check for null this object pointer.
+
2025-08-23 Eczbek <eczbek.v...@gmail.com>
PR c++/116928
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 039f6aea27ee..34ee1177e2fd 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,102 @@
+2025-08-26 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
+ for vx combine.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c: New test.
+
+2025-08-26 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
+ for vx combine.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c: New test.
+
+2025-08-25 Jakub Jelinek <ja...@redhat.com>
+
+ PR middle-end/121453
+ * gcc.dg/gomp/pr121453.c: New test.
+
+2025-08-25 H.J. Lu <hjl.to...@gmail.com>
+
+ PR tree-optimization/121656
+ * gcc.dg/pr121656.c: New file.
+
+2025-08-25 David Faust <david.fa...@oracle.com>
+
+ PR debug/121411
+ * gcc.dg/debug/ctf/ctf-array-7.c: New test.
+
+2025-08-25 Andrew Pinski <andrew.pin...@oss.qualcomm.com>
+
+ PR tree-optimization/121279
+ * gcc.dg/torture/pr121279-1.c: New test.
+
+2025-08-25 Jakub Jelinek <ja...@redhat.com>
+
+ * g++.dg/cpp26/expansion-stmt15.C: Don't expect error on
+ destructuring expansion stmts with structured binding size 0.
+ * g++.dg/cpp26/expansion-stmt21.C: New test.
+ * g++.dg/cpp26/expansion-stmt22.C: New test.
+
+2025-08-25 Jakub Jelinek <ja...@redhat.com>
+
+ PR c++/121601
+ * g++.dg/cpp26/constexpr-eh16.C: New test.
+
+2025-08-25 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/121638
+ * gcc.dg/vect/pr121638.c: New testcase.
+
+2025-08-25 Andi Kleen <a...@gcc.gnu.org>
+
+ * gcc.target/i386/shift-gf2p8affine-1.c: New test
+ * gcc.target/i386/shift-gf2p8affine-2.c: New test
+ * gcc.target/i386/shift-gf2p8affine-3.c: New test
+ * gcc.target/i386/shift-v16qi-4.c: New test
+ * gcc.target/i386/shift-gf2p8affine-5.c: New test
+ * gcc.target/i386/shift-gf2p8affine-6.c: New test
+ * gcc.target/i386/shift-gf2p8affine-7.c: New test
+
+2025-08-25 Xi Ruoyao <xry...@xry111.site>
+
+ PR target/121634
+ * gcc.target/loongarch/pr121634.c: New test.
+
+2025-08-25 Jeff Law <j...@ventanamicro.com>
+
+ * gcc.target/arm/bics_3.c: Adjust expected output
+
2025-08-23 Eczbek <eczbek.v...@gmail.com>
PR c++/116928
