https://gcc.gnu.org/g:29787cfcc2e8abfbcd89da528e014567355213bf
commit r16-3406-g29787cfcc2e8abfbcd89da528e014567355213bf
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Wed Aug 27 00:20:22 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 93 ++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/c/ChangeLog | 12 ++++++
gcc/cp/ChangeLog | 12 ++++++
gcc/fortran/ChangeLog | 11 +++++
gcc/testsuite/ChangeLog | 111 ++++++++++++++++++++++++++++++++++++++++++++++++
libstdc++-v3/ChangeLog | 42 ++++++++++++++++++
7 files changed, 282 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dde7709d5a79..451b1a0818a7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,96 @@
+2025-08-26 liuhongt <hongtao....@intel.com>
+
+ * config/i386/i386.cc (ix86_vector_costs::ix86_vector_costs):
+ Addd new memeber m_num_reduc, m_prefer_unroll.
+ (ix86_vector_costs::add_stmt_cost): Set m_prefer_unroll and
+ m_num_reduc
+ (ix86_vector_costs::finish_cost): Determine
+ m_suggested_unroll_vector with consideration of
+ reduc_lat_mult_thr, m_num_reduction and
+ ix86_vect_unroll_limit.
+ * config/i386/i386.h (enum ix86_reduc_unroll_factor): New
+ enum.
+ (processor_costs): Add reduc_lat_mult_thr and
+ vect_unroll_limit.
+ * config/i386/x86-tune-costs.h: Initialize
+ reduc_lat_mult_thr and vect_unroll_limit.
+ * config/i386/i386.opt: Add -param=ix86-vect-unroll-limit.
+
+2025-08-26 Paul-Antoine Arras <par...@baylibre.com>
+
+ * config/riscv/autovec-opt.md (*vfrdiv_vf_<mode>): Add new pattern to
+ combine vec_duplicate + vfdiv.vv into vfrdiv.vf.
+ * config/riscv/vector.md (@pred_<optab><mode>_reverse_scalar): Allow VLS
+ modes.
+
+2025-08-26 Tamar Christina <tamar.christ...@arm.com>
+
+ PR target/121290
+ * config/aarch64/aarch64.cc
+ (class aarch64_vector_costs ): Add m_loop_fully_scalar_dup.
+ (aarch64_vector_costs::add_stmt_cost): Detect invariant inner loops.
+ (adjust_body_cost): Adjust final costing if m_loop_fully_scalar_dup.
+
+2025-08-26 Paul-Antoine Arras <par...@baylibre.com>
+
+ * config/riscv/autovec-opt.md (*vfmul_vf_<mode>): Add new pattern to
+ combine vec_duplicate + vfmul.vv into vfmul.vf.
+ * config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS modes.
+
+2025-08-26 Jeff Law <j...@ventanamicro.com>
+
+ * config/riscv/riscv.cc (riscv_arg_partial_bytes): Remove name
+ from unused parameter.
+
+2025-08-26 Richard Biener <rguent...@suse.de>
+
+ * tree-vectorizer.h (vect_reduc_type): Get SLP node as argument.
+ * config/aarch64/aarch64.cc (aarch64_sve_in_loop_reduction_latency):
+ Take SLO node as argument and adjust.
+ (aarch64_in_loop_reduction_latency): Likewise.
+ (aarch64_detect_vector_stmt_subtype): Adjust.
+ (aarch64_vector_costs::count_ops): Likewise. Treat reductions
+ during scalar costing as single-cycle.
+
+2025-08-26 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/121659
+ * tree-vect-slp.cc (vect_build_slp_tree_1): Do not allow
+ matching up comparison operators by swapping if that would
+ disturb STMT_VINFO_REDUC_IDX. Make sure to only
+ actually mark operands for swapping when there was a
+ mismatch and we're not processing the first stmt.
+
+2025-08-26 Richard Biener <rguent...@suse.de>
+
+ * tree-vect-stmts.cc (vectorizable_store): Access lanes_ifn
+ only when VMAT_LOAD_STORE_LANES.
+ (vectorizable_load): Likewise.
+
+2025-08-26 Richard Biener <rguent...@suse.de>
+
+ * tree-vectorizer.h (stmt_vec_info_::reduc_vectype_in): Remove.
+ (STMT_VINFO_REDUC_VECTYPE_IN): Likewise.
+ * tree-vect-loop.cc (vect_is_emulated_mixed_dot_prod): Get
+ at the input vectype via the SLP node child.
+ (vectorizable_lane_reducing): Likewise.
+ (vect_transform_reduction): Likewise.
+ (vectorizable_reduction): Do not set STMT_VINFO_REDUC_VECTYPE_IN.
+
+2025-08-26 Jakub Jelinek <ja...@redhat.com>
+
+ PR target/121658
+ * config/i386/sse.md (<insn><mode>3 any_shift): Use const0_rtx
+ instead of GEN_INT (0).
+ (cond_<insn><mode> any_shift): Likewise. Formatting fix.
+ (<insn><mode>3 any_rotate): Use register_operand predicate instead of
+ general_operand for match_operand 1. Use const0_rtx instead of
+ GEN_INT (0).
+ (<insn>v16qi3 any_rotate): Use force_reg on operands[1]. Formatting
+ fix.
+ * config/i386/i386.cc (ix86_shift_rotate_cost): Comment formatting
+ fixes.
+
2025-08-26 Pan Li <pan2...@intel.com>
* config/riscv/vector.md (@pred_mul_plus_vx_<mode>): Add new pattern to
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3d416de541bc..815d6fb4b74f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250826
+20250827
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 589f029be3e5..bb0b8a9b541f 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,15 @@
+2025-08-26 Sandra Loosemore <sloosem...@baylibre.com>
+
+ PR middle-end/118839
+ * c-parser.cc (c_finish_omp_declare_variant): Error if variant
+ is the same as base.
+
+2025-08-26 Sandra Loosemore <sloosem...@baylibre.com>
+
+ * c-parser.cc (c_finish_omp_declare_variant): Rework diagnostic
+ code. Do not record variant if there are errors. Make check for
+ a missing "match" clause unconditional.
+
2025-08-21 Andrew Pinski <andrew.pin...@oss.qualcomm.com>
PR c/121478
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 28c1447810a6..056ee4047b52 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,15 @@
+2025-08-26 Sandra Loosemore <sloosem...@baylibre.com>
+
+ PR middle-end/118839
+ * decl.cc (omp_declare_variant_finalize_one): Error if variant
+ is the same as base.
+
+2025-08-26 Sandra Loosemore <sloosem...@baylibre.com>
+
+ * parser.cc (cp_finish_omp_declare_variant): Structure diagnostic
+ code similarly to C front end. Make check for a missing "match"
+ clause unconditional.
+
2025-08-25 Jakub Jelinek <ja...@redhat.com>
* pt.cc (finish_expansion_stmt): Implement C++ CWG3048
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 83dfc76c2bb5..06d63898651a 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,14 @@
+2025-08-26 Sandra Loosemore <sloosem...@baylibre.com>
+
+ PR middle-end/118839
+ * trans-openmp.cc (gfc_trans_omp_declare_variant): Error if variant
+ is the same as base.
+
+2025-08-26 Sandra Loosemore <sloosem...@baylibre.com>
+
+ * openmp.cc (gfc_match_omp_declare_variant): Make check for a
+ missing "match" clause unconditional.
+
2025-08-21 Steven G. Kargl <ka...@gcc.gnu.org>
PR fortran/121627
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 34ee1177e2fd..718dee0015b9 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,114 @@
+2025-08-26 Sandra Loosemore <sloosem...@baylibre.com>
+
+ PR middle-end/118839
+ * gcc.dg/gomp/declare-variant-3.c: New.
+ * gfortran.dg/gomp/declare-variant-22.f90: New.
+
+2025-08-26 Sandra Loosemore <sloosem...@baylibre.com>
+
+ * c-c++-common/gomp/append-args-1.c: Adjust expected output.
+ * g++.dg/gomp/adjust-args-1.C: Likewise.
+ * g++.dg/gomp/adjust-args-3.C: Likewise.
+ * gcc.dg/gomp/adjust-args-1.c: Likewise:
+ * gcc.dg/gomp/append-args-1.c: Likewise.
+ * gcc.dg/gomp/unprototyped-variant.c: New.
+ * gfortran.dg/gomp/adjust-args-1.f90: Adjust expected output.
+ * gfortran.dg/gomp/append_args-1.f90: Likewise.
+
+2025-08-26 Jeff Law <j...@ventanamicro.com>
+
+ * gcc.target/riscv/arch-25.c: Use wildcards to simplify/eliminate
+ dg-error directives.
+ * gcc.target/riscv/arch-ss-2.c: Similarly.
+ * gcc.target/riscv/arch-zilsd-2.c: Similarly.
+ * gcc.target/riscv/arch-zilsd-3.c: Similarly.
+
+2025-08-26 David Faust <david.fa...@oracle.com>
+
+ PR debug/121411
+ * gcc.dg/debug/ctf/ctf-array-7.c: Restrict to lp64,llp64
+ targets.
+
+2025-08-26 Torbjörn SVENSSON <torbjorn.svens...@foss.st.com>
+
+ * gcc.target/arm/unsigned-extend-2.c: Disable sched2 and sched3
+ and update function body to match.
+
+2025-08-26 liuhongt <hongtao....@intel.com>
+
+ * gcc.target/i386/vect_unroll-1.c: New test.
+ * gcc.target/i386/vect_unroll-2.c: New test.
+ * gcc.target/i386/vect_unroll-3.c: New test.
+ * gcc.target/i386/vect_unroll-4.c: New test.
+ * gcc.target/i386/vect_unroll-5.c: New test.
+ * gcc.target/i386/vect_unroll-6.c: New file.
+
+2025-08-26 Paul-Antoine Arras <par...@baylibre.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfrdiv.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: Add support for reverse
+ variants.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
+ reverse variants.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c: New test.
+
+2025-08-26 Tamar Christina <tamar.christ...@arm.com>
+
+ PR target/121290
+ * gcc.target/aarch64/pr121290.c: New test.
+
+2025-08-26 Paul-Antoine Arras <par...@baylibre.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmul.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c: Adjust scan
+ dump.
+ * gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c: Likewise.
+
+2025-08-26 Richard Earnshaw <rearn...@arm.com>
+
+ * gcc.target/arm/bics_3.c: Add some additional tests that
+ cannot be folded to a bit manipulation.
+
+2025-08-26 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/121659
+ * gcc.dg/vect/pr121659.c: New testcase.
+
+2025-08-26 Jakub Jelinek <ja...@redhat.com>
+
+ PR target/121658
+ * gcc.target/i386/pr121658.c: New test.
+
2025-08-26 Pan Li <pan2...@intel.com>
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index ed99f9f1ea4c..07edcd5e0a66 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,45 @@
+2025-08-26 Patrick Palka <ppa...@redhat.com>
+
+ * include/std/ranges (__detail::_CachedPosition): Remove
+ additional size constraint on the offset-based partial
+ specialization.
+
+2025-08-26 Tomasz Kamiński <tkami...@redhat.com>
+
+ PR libstdc++/90192
+ * include/bits/stl_vector.h (vector<T>::_M_fill_append): Declare.
+ (vector<T>::fill): Use _M_fill_append instead of _M_fill_insert.
+ * include/bits/vector.tcc (vector<T>::_M_fill_append): Define
+ (vector<T>::_M_fill_insert): Delegate to _M_fill_append when
+ elements are appended.
+ * testsuite/23_containers/vector/modifiers/moveable.cc: Updated
+ copycount for inserting at the end (appending).
+ * testsuite/23_containers/vector/modifiers/resize.cc: New test.
+ * testsuite/backward/hash_set/check_construct_destroy.cc: Updated
+ copycount, the hash_set constructor uses insert to fill buckets
+ with nullptrs.
+
+2025-08-26 Tomasz Kamiński <tkami...@redhat.com>
+
+ * include/bits/move.h (std::__like_impl, std::__like_t): Make
+ available in c++11.
+ * include/std/functional (std::_Indexed_bound_arg)
+ (std::_Bound_arg_storage, std::__make_bound_args): Define.
+ (std::_Bind_front, std::_Bind_back): Use _Bound_arg_storage.
+ * testsuite/20_util/function_objects/bind_back/1.cc: Expand
+ test to cover cases of 0, 1, many bound args.
+ * testsuite/20_util/function_objects/bind_back/111327.cc: Likewise.
+ * testsuite/20_util/function_objects/bind_front/1.cc: Likewise.
+ * testsuite/20_util/function_objects/bind_front/111327.cc: Likewise.
+
+2025-08-26 Tomasz Kamiński <tkami...@redhat.com>
+
+ * include/std/stop_token (__variant::_Never_valueless_alt): Declare.
+ (__variant::_Never_valueless_alt<std::stop_token>)
+ (__variant::_Never_valueless_alt<std::stop_source>): Define.
+ * include/std/thread: (__variant::_Never_valueless_alt): Declare.
+ (__variant::_Never_valueless_alt<std::jthread>): Define.
+
2025-08-21 Jonathan Wakely <jwak...@redhat.com>
PR libstdc++/121496
